[paper] Pulsed I-V on TFETs: Modeling and Measurements

Pulsed I-V on TFETs: Modeling and Measurements
Quentin Smets, Anne Verhulst, Ji-Hong Kim, Jason P. Campbell, David Nminibapiel, Dmitry Veksler, Pragya Shrestha, Rahul Pandey, Eddy Simoen, David Gundlach, Curt Richter, Kin P. Cheung, Suman Datta, Anda Mocuta, Nadine Collaert, Aaron V.-Y. Thean, and Marc M. Heyns
in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1489-1497, April 2017
doi: 10.1109/TED.2017.2670660

Abstract: Most experimental reports of tunneling field-effect transistors show defect-related performance degradation. Charging of oxide traps causes Fermi-level pinning, and Shockley–Read–Hall (SRH)/trap-assisted tunneling (TAT) cause unwanted leakage current. In this paper, we study these degradation mechanisms using the pulsed I-V technique. Our simulations show pulsed I-V can fully suppress oxide trap charging, unlike SRH and TAT. We discuss several circuit-related pitfalls, and we demonstrate improved transfer characteristics by suppressing oxide trap charging using cryogenic pulsed I-V [read more...]

[paper] III-V Channel Double Gate FETs

Compact Modeling of Charge, Capacitance, and Drain Current
in III-V Channel Double Gate FETs

C. Yadav; M. Agrawal; A. Agarwal; Y. S. Chauhan

in IEEE Transactions on Nanotechnology , vol.PP, no.99, pp.1-1
doi: 10.1109/TNANO.2017.2669092

Abstract: In this paper, we present a surface potential based compact modeling of terminal charge, terminal capacitance, and drain current for III-V channel double gate field effect transistor (DGFET) including the effect of conduction band nonparabolicity. The proposed model is developed accounting for the 2-D density of states and includes the effect of quantum capacitance associated with the low density of states channel material. In addition, model incorporates contribution of the first two subbands and efficiently captures the step like behavior appearing in the gate capacitance and trans-conductance with population of the higher sub-bands. The behavior of bias dependent terminal capacitances and drain current are verified with the numerical simulation data of InGaAs channel DGFET and shows a close agreement with the simulation data [read more...]

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 

INFOS 2017

June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:

• High-k dielectrics, metal gate materials and SiO2 for future scaling
• Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
• Stacked dielectrics for non-volatile memory (flash, nc-Si)
• Dielectrics for resistive switching memories and spin memories
• Dielectrics for DRAM and MIM
• Low-k dielectrics
• Semiconductors on insulators
• Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
• Surface cleaning technologies
• Physics and chemistry of dielectrics and defects
• Characterization techniques for dielectrics and interfaces
• Electrical reliability, leakage and modelling
• Modelling of atomic structure of dielectrics, interfaces and thin films
• Topological insulators
• Ferroelectrics and functional oxides
• Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
• Dielectrics for photonics and sensing

Semiconductor Devices Characterization Seminar

Technical Seminars addressing the challenges of CMOS, Power and RF

semiconductor device measurement and modeling 

Agilent and it´s 25 collaborative partners invite you to attend this complimentary technical seminar on characterization and modeling of semiconductor devices. Two tracks in parallel will address the needs for:

• Small scale silicon industry
• Power silicon industry and RF Power

Common topics to both Tracks:

• Live demonstration of GaN device characterization flow: DC I-V characteristic extraction, RF Power measurement, Spice models creation for further usage in design stage.

CMOS Track:

• Accurate and repeatable on-the-wafer device extraction – Cascade Microtech
• DC characterization for emerging nano-technologies
• Flicker Noise and Random Telegraph Noise
• Spice model libraries optimization for dedicated application

Power & RF Power Track:

• High Power Devices measurement
• III-V devices spice model (DynaFET)
• Nonlinear Component characterization
• Non-50ohm Load Pull solution – Maury

Where/when:
To obtain the detail agenda of the nearest session, please select one of the locations below.

Country	City	Date	More Information
FR	Grenoble	18 September 2014	Register here
FI	Helsinki	23 September 2014	Register here
DE	Munich	30 September 2014	Register here
DE	Dresden	2 October 2014	Register here
CH	Lausanne	14 October 2014	Register here
BE	Leuven	16 October 2014	Register here
NL	Eindhoven	17 October 2014	Register here
SW	Goteborg	28 October 2014	Register here
UK	Cambridge	30 October 2014	Register here
FR	Les Ulis	6 November 2014	Register here

 

 

[Final Program] 11th International Workshop on Compact Modeling

11th International Workshop on Compact Modeling (IWCM 14)

January 23 (Thursday), 2014

Suntec Singapore Convention and Exhibition Centre (Room 309)

Workshop Program

9:00-9:10am Welcome address
Mansun Chan (workshop chair)

Session I: Modeling for Compact Semiconductor
Session Chair: Lining Zhang

9:10-9:35am Challenges and Prospects of Compact Modeling for Future Generation III-V/Si Co-integrated ULSI Circuit Design
Xing Zhou, Siau Ben Chiah, Binit Syamal, Hongtao Zhou, Arjun Ajaykumar, and Xu Liu; Nanyang Technological University, Singapore
9:35-10:00am A Large Signal Model for InP/InGaAs Double Heterojunction Bipolar Transistors
Yan Wang and Yuxia Shi; Tsinghua University, China
10:00-10:25am Analytical Modeling for AlGaN/GaN HEMTs
Aixi Zhang, Lining Zhang, Zhikai Tang, Xiaoxu Cheng*, Yan Wang*, Kevin J. Chen, and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China; *Tsinghua University, China

10:25-10:40am Break

Session II: Non-Classical Device Modeling and Platform
Session Chair: Xing Zhou

10:40-11:05am Developing i-MOS as a Compact Model Standardization Platform
Lining Zhang and Mansun Chan; The Hong Kong University of Science and Technology, Hong Kong, China
11:05-11:30am An Analytic Model for Nanowire Tunnel-FETs
Ying Liu, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China
11:30-11:55am A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET
Xiangyu Zhang, Jin He, Mansun Chan*, Caixia Du**, Yun Ye, Wei Zhao, Wen Wu and Wenping Wang; Peking University Shenzhen SOC Key Laboratory, China; *The Hong Kong University of Science and Technology, Hong Kong, China; **Shenzhen Huayue Teracale Chip Electronic Limited Co., China

11:55am-2:00pm Lunch

Session III: Power Device Modeling
Session Chair: Young June Park

2:00-2:25pm Compact Modeling of the Reverse Recovery Effect in LDMOS Body Diode (Invited)
M. Miyake; Hiroshima University, Japan
2:25-2:50pm Compact Modeling of the SiC IGBT Including the Switching at High Temperature
K. Matsuura, M. Miura-Mattausch, M. Miyake and H. J. Mattausch; Hiroshima University, Japan
2:50-3:15pm Experimental Verification of Power MOSFET Model under Switching Operations
A. Saito, M. Miura-Mattausch, M. Miyake, T. Umeda and H.J. Mattausch; Hiroshima University, Japan

3:15-3:30pm Break

Session IV: Reliability Modeling
Session Chair: Jin He

3:30-3:55pm 3D Monte Carlo Reaction-Diffusion Simulation Framework to model Time Dependent Dielectric Breakdown in BEOL Oxide
Seong Wook Choi and Young June Park; Seoul National University, Korea
3:55-4:20pm Development of NBTI and Channel Hot Carrier (CHC) Effect Models and their Application for Circuit Aging Simulation
Chenyue Ma, Hans Jürgen Mattausch, Kazuya Matsuzawa*, Seiichiro Yamaguchi*, Teruhiko Hoshida*, Masahiro Imade*, Risho Koh*, Takahiko Arakawa* and Mitiko Miura-Mattausch; Hiroshima University, Japan; * Semiconductor Technology Academic Research Center, Japan
4:20-4:45pm Modeling of the Surface Charges on Au Electrode Including Pseudocapacitance
Jooseong Kwon, Intae Jeong, Sungwook Choi and Young June Park; Seoul
National University, Korea

4:45-4:55pm Closing Remarks
Hans Juergen Mattausch (workshop co-chair)