Oct 14, 2016

FOSDEM 2017 EDA Devroom Call for Participation



This is the call for participation in the FOSDEM 2017 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 5 February 2017 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
  • Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  • Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
  • Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g.Yosys)
  • Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks. Have a look at last year's event for a taste of what the EDA devroom is about.

The submission process
Please submit your proposals at 
before 1 December 2016.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Electronic Design Automation (EDA) devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates
  • 1 December 2016: deadline for submission of proposals
  • 11 December 2016: announcement of final schedule
  • 5 February 2017: devroom day
Recordings
The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list

Feel free to subscribe to the mailing list of the EDA devroom to submit ideas, ask questions and generally discuss about the event.

Spread the word!
This is the third EDA devroom at FOSDEM. The first two were very well received. Let's make sure as many projects and developers as possible are present. Thanks!

Oct 13, 2016

[call for papers] 1st EDTM 2017

Submission deadline: November 4th, 2016
Camera ready, one page text and one page figures

At Toyama International Conference Center, Toyama, Japan
February 28th to March 2nd, 2017

Why EDTM has been started: System performance continues to grow, even though device scaling is saturated. Based on strong manufacturing technologies, Asia has strong potential to take an initiative for system integration. Deep-dive discussions among technical communities on materials, processes, and devices are aimed to accelerate manufacturing innovations through this forum.

1. Technical sessions

EDTM 2017 and beyond will have a strong specific technical focus, and this year’s focus being on devices and process technologies for advanced applications, IoE (Internet of Everything) and related low-power devices, advanced memories, sensors, actuators, MEMS, bio.-chips, passive devices, and all types of (exploratory) devices related to advance applications and IoE. Papers/Posters on materials and processes for enabling above-menHoned devices building in heterogeneous integration such as 2.1, 2.5 and 3D structures using wafer-level packaging process (e.g.) are of great focus. EDTM aims for highest quality, and all papers accepted would be subject to IEEE-EDS standard review processes and conference publishing guidelines. Accepted and presented papers will be published in EDTM proceedings. A selected number of high impact EDTM papers would be invited for the consideration of publication in the IEEE Journal of Electron Devices Society (J- EDS) as extended version of EDTM conference papers following the IEEE publication policy and J-EDS author-guidelines.

2. Education

  • Tutorials: We will provide both the basic and advanced programs. Basic program will be presented in local language.
  • Poster sessions: Primarily intended for young engineers and students. The best poster will be awarded in the conference.
  • Short courses: Will bring high level programs.

3. Exhibition

Given the strong semiconductor manufacturing base in Asia, we intend to offer exhibits that will demonstrate products and technology. All of the exhibitors will have an opportunity to offer technical insight and share their knowhow. Moreover, we hope to offer Forum Making Session to engage and allow deeper discussions between device, material, and equipment engineers and technologists.

Papers in the following areas are requested by Subcommittee on:

  • Devices and Manufacturing for “Cloud and Edge”
  • Packaging and Manufacturing for “Cloud and Edge”
  • Process, Tools, and Manufacturing
  • Semiconductor Materials
  • Reliability & Modeling (including compact/SPICE)







IEDM 2016 Session 7: Modeling and Simulation Advanced Numerical and Compact Models

IEDM 2016 Session 7

Monday, December 5, 1:30 p.m. Continental Ballroom 7-9 
Co-Chairs: Denis Rideau, STMicroelectronics 
Xing Zhou, Nanyang Technological University

1:35 PM 
7.1 A Novel Synthesis of Rent's Rule and Effective-Media Theory Predicts FEOL and BEOL Reliability of Self-Heated ICs, W. Ahn, H. Jiang, S.H. Shin and M. Alam, Purdue University

2:00 PM 
7.2 New Approach for Understanding "Random Device Physics" from Channel Percolation Perspectives: Statistical Simulations, Key Factors and Experimental Results, Z. Zhang, Z. Zhang, R. Wang, X. Jiang, S. Guo, Y. Wang, X. Wang*, B. Cheng*, A. Asenov* and R. Huang, Peking University, *Synopsys

2:25 PM 
7.3 Oxide-Based Analog Synapse: Physical Modeling, Experimental Characterization, and Optimization, B. Gao, H. Wu, J. Kang*, H, Yu**, H. Qian, Tsinghua University, *Peking University, **Southern University of Science and Technology

2:50 PM 
7.4 Extending the Bounds of Performance in E-mode p-channel GaN MOSHFETs, A. Kumar and M. De Souza, The University of Sheffield

3:15 PM 
7.5 NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs, O. Rozeau, S. Martinie, T. Poiroux, F. Triozon, S. Barraud, J. Lacord, Y.-M. Niquet*, C. Tabone, R. Coquand, E. Augendre, M. Vinet, O. Faynot, and J.-C. Barb, CEA-Leti, *CEA-INAC

3:40 PM 
7.6 A Physics-Based Compact Model for Material- and Operation-Oriented Switching Behaviors of CBRAM, Y. Zhao, J. Hu, P. Huang, F. Yuan*, Y. Chai*, X. Liu and J. Kang, Peking University, *The Hong Kong Polytechnic University

4:05 PM 
7.7 Multi-Domain Compact Modeling for GeSbTe-based Memory and Selector Devices and Simulation for Large-scale 3-D Cross-Point Memory Arrays, N. Xu, J. Wang, Y. Deng, Y. Lu, B. Fu, W. Choi, U. Monga*, J. Jeon*, J. Kim*, K.-H. Lee* and E. S. Jung*, Samsung Semiconductor Inc., *Samsung Electronics

[read more...]

Oct 12, 2016

Compound Semiconductor Technical Committee Meeting

SEMI® International Standards Program
Compound Semiconductor Technical Committee Meeting
Fraunhofer IISB, Schottkystrasse 10, D-91058 Erlangen, Germany
Thu 13th October 2016 14:00 to 16:30

Co-chairs:
• Dr. Arnd-Dietrich Weber, SiCrystal
• N.N. 

Agenda: European Compound Semiconductor Committee Meeting
Task Force meetings – tbd
14:00 Welcome and Self-Introductions all
14:05 SEMI Standards Overview and Legal Reminders SEMI Staff
14:10 Review of the minutes and action items from the previous meeting SEMI Staff
14:15 Task Force Reports (~5 minutes each)
SiC-Task Force A. Weber
Status M55 5-year review (doc 4689)
Status M81 5-year-review (doc 6015)
Contactless Capacitive Resistivity Task Force W. Jantz
14:30 Discussion and approval of doc 4689 (M55 review) for ballot A. Weber
15:00 5-Year-Review of published documents
5-year-review of M54 (Guide for semi-insulating GaAs parameters): discuss and
approve TFOF and SNARF U. Kretzer
dentification and discussion of action items all
15:30 Compound Materials Liaison Reports
North America
Japan SEMI Staff
15:45 Any Other Business / Questions A. Weber
16:00 Next Meetings
16:15 Adjourn 

Lectures on Electromagnetism https://t.co/nxi9p90Cte #papers


from Twitter https://twitter.com/wladek60

October 12, 2016 at 10:55AM
via IFTTT

Oct 10, 2016

[website] Open Circuit Design Software


Visit the Open Circuit Design Software to learn more about the major electronic design automation (EDA) tools hosted by Open Circuit Design:
  • Magic, the VLSI layout editor, extraction, and DRC tool
  • XCircuit, the circuit drawing and schematic capture tool
  • IRSIM, the switch-level digital circuit simulator
  • Netgen, the circuit netlist comparison (LVS) and netlist conversion tool
  • Qrouter, the over-the-cell (sea-of-gates) detail router
  • Qflow, a complete digital synthesis design flow using open-source software and open-source standard cell libraries
  • PCB, the printed circuit board layout editor
[More about Open Circuit Design Software]

[paper] Well-Posed Models of Memristive Devices

Well-Posed Models of Memristive Devices
(Submitted on 15 May 2016)
Existing compact models for memristive devices (including RRAM and CBRAM) all suffer from issues related to mathematical ill-posedness and/or improper implementation. This limits their value for simulation and design and in some cases, results in qualitatively unphysical predictions. We identify the causes of ill-posedness in these models. We then show how memristive devices in general can be modelled using only continuous/smooth primitives in such a way that they always respect physical bounds for filament length and also feature well-defined and correct DC behaviour. We show how to express these models properly in languages like Verilog-A and ModSpec (MATLAB). We apply these methods to correct previously published RRAM and memristor models and make them well posed. The result is a collection of memristor models that may be dubbed "simulation-ready", i.e., that feature the right physical characteristics and are suitable for robust and consistent simulation in DC, AC, transient, etc., analyses. We provide implementations of these models in both ModSpec/MATLAB and Verilog-A.

Subjects: Emerging Technologies (cs.ET); Computational Engineering, Finance, and Science (cs.CE)
Cite as: arXiv:1605.04897 [cs.ET]
(or arXiv:1605.04897v1 [cs.ET] for this version)