Call for IJNM Papers: Modeling of high-frequency silicon transistors

Silicon transistors (STs) have been the workhorse of the electronics industry ever since its inception. Although STs historically have been used primarily in digital and low-frequency analog applications, they increasingly are being adopted for high-frequency analog purposes as well. This trend is fueled by the introduction of new fabrication methods, novel materials, and transistor architectures that permit aggressive downscaling into the nanometer regime. Along these lines, considerable attention currently is being devoted to the FinFET, which is an innovative multiple-gate field effect transistor offering the important advantage of being compatible with conventional planar CMOS technology.

Modeling and simulation are indispensable in the development of high-frequency STs. Indeed, ST models and simulations provide indispensable feedback for improving device fabrication processes and serve as a valuable tool for optimizing circuit designs. Unfortunately, the predictive power of modeling and simulation techniques for STs for digital and low-frequency applications oftentimes diminishes when applied to high-frequency analog STs. For modeling and simulation methods to drive the development of high-frequency ST technology, they must adapt as well. 

The purpose of this Special Issue is to publish high-quality contributions addressing the modeling and simulation of high-frequency STs. A wide range of topics will be covered, ranging from bipolar to ?eld effect transistors and from linear to noise and non-linear models. Although the main focus of the Special Issue will be the extraction of high-frequency models, papers addressing other aspects of ST modeling will be considered as well. This issue will contain both invited and contributed papers. Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/ (ISSN)1099-1204/homepage/ForAuthors.html.

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Guest Editors:

• Dr. Giovanni Crupi
  University of Messina, Italy
  E-mail: crupig@unime.it
• Prof. Dominique Schreurs
  University of Leuven, Belgium
  E-mail: dominique.schreurs@esat.kuleuven.be
• Prof. Alina Caddemi
  University of Messina, Italy
  E-mail: acaddemi@unime.it

Manuscript submission deadline: April 30, 2013

[mos-ak] [2nd announcement] Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee and the workshop sponsors MunEDA and Tanner EDA, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich <http://www.mos-ak.org/munich_2013/>

Venue:

Lehrstuhl fur Technische Elektronik

Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>

Technische Universitat Munchen 

Arcisstr. 21 D-80333 Munchen

Important Dates:

• Call for Papers - Jan. 2013
  
• 2nd Announcement - March 2013
  
• Final Workshop Program - March, 2013
  
• MOS-AK/GSA Workshop - April 11-12, 2013

R&D topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies

Postworkshop publications;

selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Extended MOS-AK/GSA Committee

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DEVSIM is now open source

Juan Sanches of Devsim LLC (Austin, Texas) announced:

DEVSIM is now open source 

The source code for my device simulation software, DEVSIM, is now available for download. The core engine is released under the LGPL 3.0. I hope this software will be useful to the TCAD community and it is available for download from github:

https://github.com/devsim/devsim?goback=.gde_164417_member_223659152

Great. Looks very interesting. A lot of good code. Anyone here by chance has any experience with it?

NANO 2013

Symposium on Nanostructured Materials to be held May 21-22, 2013 at the University of Rzeszow, Poland. The Symposium will be a major event during the grand opening of the Center for Microelectronics and Nanotechnology. This conference is devoted to the current trends in research on layer-structured materials and one-dimensional nanomaterials. Emphasis will be placed on the state-of-the-art metrology for detecting defects and impurities using modern TEM, SIMS, and Nano-Raman methods etc. Specific areas of interest include:

• MBE technology, 
• nanopatterning, 
• nanolithography, 
• photolithography and electron lithography for the production of integrated circuits, 
• magneto-transport at low temperatures, 
• optical properties of nanostructures, 
• interaction between academic and industrial research
  (instrument manufacture, IC and optoelectronics industry, and materials suppliers).

[read more...]

[mos-ak] Live webcast - MQA: The Golden Standard for Device Model Validation

 

MQA: The Golden Standard for Device Model Validation  Webcast Register now >
Agilent Technologies invites you to our live webcast so that you can stay up to date with the latest technologies and solutions. When: 19th March 10:30 (CET) Where: Online       Why is this webcast important? Whether you are a Foundry or IDM creating models, or a design house using device models, it is important to understand model behaviour and asses quality. Foundries/IDMs need to comprehensively and effectivley asses the quality of device models, and take steps to assure their behaviour for the technology of interest. Design houses need to validate device models, and understand their behaviour in the regions of interest, prior to indroducing to the design teams. It is important for Design Houses to understand where errors exist in Foundry supplied libraries, model and document their behaviour, and assure operation in the simulation environment. MQA provides this functionality for Foundries, IDMs and fab-less Design Houses, and provides a sophisticated automated Report Generation feature to document results.       Who should view this webcast? Modeling teams that create device models at Foundries/IDMs, foundry interface groups at Design Houses, IC designer & manger who need to evaluate new Foundry technology.  Register Now           Presenter: Janice Deng         Janice Deng graduated from Peking University in Microelectronic, and went on to get an Engineering diploma at ESIEE, France. In 2008, she joined Accelicon , as an application engineer supporting MBP and MQA worldwide.                   Presenter: Cedric Pujol         Cedric Pujol received his Electronic Diploma at Engineering School INP Grenoble France in 1997. He has worked 7 years at ST Microelectronics, in Central R&D. He developed his skills on Device Modeling through various positions : Design Kit development for Analog and RF, Design tool strategy choice for ST. Cedric joined Xpedion then Agilent where he is now leading the RFIC pre-sales activity in Europe as well as Device Modeling solution.

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Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond

From EDN:

Industry Need for Continued Scaling
Technological advances in transistor scaling have had a dramatic effect on consumer electronics and their corresponding use cases. In 1973, Motorola developed the first mobile phone, which weighed 2.5 pounds, was 9 inches long, had limited battery life and only allowed users to make and receive calls. Fast forward to today's mobile devices that fit in the palm of your hand, with batteries that last all day and more computing power than ever thought possible.
While it has taken 40 years to come this far, innovation has been exceptionally rapid over the course of the past 10 years, and consumer expectations have accelerated at a similar pace. What sort of features and computing capabilities will we expect of our mobile devices five years from now? How about in 10 years? Future improvements largely hinge on the industry's ability to continue on the path of Moore's Law by producing ever-smaller transistors with ever-greater performance. Satisfactory scaling fulfills two core requirements: the need for smaller transistors that reduce costs and a parallel need for improved performance and lower power consumption.
To date, transistor scaling has continued in accordance with Moore's Law down to 32 nm. Engineering challenges, however, are forcing chipmakers to compromise performance and power efficiency in order to reach smaller nodes - unless they switch to new technologies that help better solve these challenges. Today, the semiconductor industry is starting to deploy such new technologies, largely relying on "fully-depleted" transistors for continued scaling and performance gains.
Fully Depleted Silicon Technology
A fully depleted (FD) transistor can be planar or tri-dimensional. In each case, in direct contrast with other technologies commonly used today, the current between source and drain is allowed to flow only through a thin silicon region, defined by the physical parameters of the transistor.
In the planar design of fully depleted technology, transistors are built flat on the silicon. For the three-dimensional alternative, manufacturers fabricate thin vertical "fins" of silicon in which current will flow from source to drain. Additionally, FD transistors can eliminate the need for implanting "dopant" atoms into the channel. These improvements help chipmakers secure gains in both energy efficiency and performance that are required from scaling silicon technology.

Figure 1: Top Left (1a): Cross-section of a conventional MOS transistor on bulk silicon, Top right (1b): Cross-section of a planar fully-depleted transistor (FD-SOI), Bottom (1c): Perspective view of a FinFET (one fin shown here), silicon-on-insulator and bulk silicon flavors. (*) Note: PTS in the bottom right diagram is Punch Through Stopper, which is a heavily doped barrier layer at the bottom of the fin. S is Source, G is Gate, D is Drain of CMOS transistors. Notional views only; dimensions are not to scale.

READ MORE in the original post.

IBM, GF, and Samsung offer a glimpse of chipmaking's future

Below is a slide showing GF' process tech roadmap for the next little while:

[read more...]

13. ITG/GMM-Fachtagung Analog 2013

13. ITG/GMM-Fachtagung Analog 2013
4. - 6. März in Aachen
Entwicklung von Analogschaltungen mit CAE-Methoden

Die Registrierung ist eröffnet!

Call For Papers:

Programm und Anmeldeformular:

Why- and how- to integrate Verilog-A compact models in SPICE simulators

Article first published online: 20 JUL 2012
by Maria-Anna Chalkiadaki1, Cédric Valla2, Frédéric Poullet2 and Matthias Bucher1 (1. Department of Electronic and Computer Engineering, Technical University of Crete, 73100 Chania, Greece and 2. Dolphin Integration, 38242 Meylan, France)

SUMMARY: This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models’ Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models.

Synopsys Accelerates Adoption of FinFET Technology with Delivery of Production-Proven Design Tools and IP

From YahooFinance: (see their page for the original post)



Synopsys, Inc. (SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced immediate availability of its comprehensive solution for FinFET-based semiconductor designs. The solution includes a range of DesignWare^®Embedded Memory and Logic Library IP; silicon-proven design tools from the Galaxy^™ Implementation Platform; and foundry-endorsed extraction, simulation and modeling tools. It also includes TCAD and mask synthesis products used by foundries for FinFET process development. The three-dimensional structure of FinFET devices represents a significant change in transistor manufacturing that impacts design implementation tools, manufacturing tools and design IP. Developed over a period of five years through engineering collaboration with leading foundries, research institutes and early adopters, Synopsys' FinFET solution delivers production-proven technologies to manage the change from planar to 3-D transistors. The full-line solution provides a strong foundation of EDA tools and IP needed to accelerate deployment of FinFET technology which offers improved power, performance and area for semiconductor designs.
"Synopsys continues to make significant investments to develop a complete solution for adoption of new process geometries and devices, including FinFETs," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Synopsys' extensive collaboration with all the partners within the FinFET ecosystem, including foundries, early adopters and research institutions, allows us to deliver best-in-class technologies and to enable the market to realize the full potential of this new transistor design."
"With our new 14nm-XM offering, we have accelerated our leading-edge roadmap to deliver a FinFET technology optimized for the expanding mobile market," said Gregg Bartlett, senior vice president, chief technology officer at GLOBALFOUNDRIES. "Collaboration with partners has been a key element of our ability to deliver this innovative FinFET solution. We have collaborated early with Synopsys in multiple areas, including modeling of the FinFET devices in HSPICE. We continue our collaboration to accelerate adoption of FinFET technology for our mutual customers."
"Our FinFET collaboration with Synopsys is key to maintaining our semiconductor leadership position," said Dr. Kyu-Myung Choi, senior vice president of System LSI Infrastructure Design Center, Samsung Electronics Co., Ltd. "Our foundry and semiconductor design expertise, combined with Synopsys' broad EDA tool and IP development experience enabled us to address FinFET-related challenges effectively. We continue to engage in strong collaboration to maximize the benefits of FinFET technology."
"Very early on, we successfully demonstrated the power and performance benefits of using FinFET 3-D transistors," said Dr. Chenming Hu, distinguished professor of microelectronics at University of California, Berkeley, widely regarded as the pioneer of FinFET technology. "To make these demonstrations possible, my team worked closely with Synopsys R&D on a number of areas including device simulation. We continue to collaborate with Synopsys to deliver more innovations for FinFET deployment."
FinFET-ready IP  Working closely with leading foundries for more than five years enabled Synopsys to gain design expertise and a deep understanding of IP architectures. This close collaboration has resulted in the successful deployment of Synopsys' DesignWare Embedded Memory and Logic Library IP solutions on FinFET to key customers. A broader range of IP is planned for development in 2013. The DesignWare Embedded Memory and Logic Library IP is architected to achieve the full benefits of the FinFET technology, delivering superior results in the areas of performance, leakage and dynamic power, and low voltage operation.
FinFET-ready Design Tools   The shift from planar to FinFET-based 3-D transistors is a significant change that requires close R&D collaboration among tool developers, foundries and early adopters to deliver a strong EDA foundation.  Developed through a multi-year collaboration with FinFET ecosystem partners, Synopsys' solution accelerates time to market of FinFET-based designs.  The comprehensive solution includes IC Compiler for physical design, IC Validator for physical verification, StarRC^™ for parasitic extraction, SiliconSmart for characterization, CustomSim^™ and FineSim for FastSPICE simulation and HSPICE^® for device modeling and circuit simulation.
FinFET-ready Manufacturing Tools    The small geometries and 3-D nature of FinFETs require new approaches to optimize device performance and leakage, and to address the effect of process variations. Target device performance and leakage is achieved through the optimization of the fin geometry, stress engineering and other factors. Process variations stem from random dopant fluctuations, line edge roughness, layout-induced stress and other sources, which together impact device and circuit performance. Synopsys has been collaborating with foundries on the Sentaurus^™ TCAD and Proteus^™ mask synthesis products to address these issues. The Sentaurus product line enables foundries to optimize FinFET processing and design devices that meet the performance and leakage targets while mitigating the impact of process variation. The Proteus product line provides foundries with a comprehensive solution for performing full-chip proximity corrections.

[mos-ak] C4P: Spring MOS-AK/GSA Workshop in Munich; April 11-12, 2013

Together with the workshop host, Prof. Dr. Doris Schmitt-Landsiedel, Lehrstuhl fur Technische Elektronik, TUM and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the spring MOS-AK/GSA Workshop in Munich <http://www.mos-ak.org/munich_2013/>

Venue:

Lehrstuhl fur Technische Elektronik

Room: 5325, 5th floor <http://www.lte.ei.tum.de/index.html>

Technische Universitat Munchen 

Arcisstr. 21 D-80333 Munchen

Important Dates:

• Call for Papers - Jan. 2013
  
• 2nd Announement - Feb. 2013
  
• Final Workshop Program - March, 2013
  
• MOS-AK/GSA Workshop - April 11-12, 2013
  

R&D topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies

Extended MOS-AK/GSA Committee

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SPICE Models No Longer Only A Foundry’s Worry

A nice post at chipdesign:

By Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc.

 

SPICE Models Play a Critical Role in Both Modeling and Design Communities

Circuit designers work with foundry libraries to evaluate a foundry process before they run real circuit designs. It, therefore, becomes necessary to understand the models and use them properly. Complexities of modern libraries have made it inefficient or almost impossible to understand them by browsing into the files.

A library can easily contain many different sections besides core models in a macro (sub-circuit) format, such as multiple corner model sections, statistical model sections, mismatch model components, models for layout dependent effects and reliability models. Without a good understanding of those details, simulations by combining those model sections may lead to inaccurate results.

Second, foundry models often are not built for specific applications. Design companies are investing in SPICE models by doing model validations, customizing models for specific needs or even building their own models. High-end systems-on-chip (SoCs) are now integrating more functionalities and may have different operation modes, evaluated by performance, power, area, lifetime, cost (yield) and time to market.

Design specifications are tougher, but the room to maneuver has shrunk. One set of generic models can’t meet the requirements for all different applications. Thus, it’s worthwhile for design companies to identify the real needs of their applications, then work with foundries or third parties or build their own capabilities to make model libraries more application specific and provide more value for their designs.

Third, the key motivation for a circuit designer to understand foundry model libraries is the impact of process variations on circuit performance and yield. Although process engineers have tried different ways to mitigate variation sources during manufacturing, some remain in a design that are fundamental and must be managed during different design stages, including global and local random variations or LDE.

Designers can only cross their fingers if they do not know the possible results before tapeout. Modeling engineers have figured out ways to model those systematic and random variation effects. The next step is to apply that information and analyze the impact to a design.

Strain engineering improves device performance, but leads to the strong layout dependence of device characteristics. Designers then need to consider the impact of LDE during pre-layout design, layout design, LVS extraction and post-layout verifications. Understanding the LDE based on the models would help designers better optimize area versus performance, and reduce differences between pre- and post-layout designs to shorten design time.

Increasing random variations, especially the local mismatch for paired transistors, affect the final chip yield and performance. Traditional PVT analysis and selective Monte Carlo analysis give limited information that can help achieve chip’s functionalities, but not the possible yield or performance distributions.

A reliable and practical design for yield (DFY) flow with fast and accurate statistical simulation engine is required. Moreover, before using DFY tools for yield analysis targeting yield and performance trade-off, designers need to know how corner models and statistical models are defined. Otherwise analysis results, based on improper use of the variation models, will offer the wrong direction for design optimizations. 

... read more at the source...

Compact model Engineer job in IBM India (Bangalore)

For nearly 30 years, IBM has been at the forefront of technology innovation for semiconductor solutions. IBM has transformed semiconductor design and manufacturing with world-renowned research and development. Our contributions are recognized throughout the industry. Reduced Instruction Set Computing (RISC), Copper Interconnects, Silicon Germanium (SiGE) and Silicon on Insulator (SOI) are some of the innovations that have come from IBM. 

IBM Semiconductor Research & Development centre is expanding its operations by opening a CMOS development & enablement group at ISL, Bangalore. Mentioned below are some of the key areas which will be operational out of India centre.

Compact Model Development in Bulk, SOI & SiGe Technology

• Develop Core model Extraction for FET, HBT, passive devices
• Develop Extraction Algorithms (Genetic, IC-CAP, MATLAB)
• Model Build in BSIM, PSP, MEXTRAM & HiCUM
• Enable SPECTRE, HSPICE, POWERSPICE, VERILOG-A Models for Leading Design Environments
• Enable IBM Server & High-Speed-Serial Group and other Leading Customers to Design in IBM Technology

Skills important to the area:

• Knowledge of BSIM, UTMOST and / or IC-CAP MOSFET parameter Extraction
• Knowledge of Hspice / Spectre and / or PowerSpice
• Basic understanding of semiconductor device physics and operation
• Cadence Design systems and tool for programming, layout and simulation
• Software Skills - C, Java, Scripting and/or other automation languages
• We are looking for people holding a PhD / MTech / BTech in the ECE/EE/CSE disciplines.

Relevant vacancies:

SWG-0050763	Compact Model Engineer

How to apply:

Go to the career section in their homepage...

New IC-CAP with GaN and Python support

Some news from EDN:


Agilent Technologies recently announced a new version of IC-CAP (integrated circuit characterization and analysis platform) for high-frequency device characterization and modeling, offering parameter extraction, data analysis, instrument control and interface responsiveness. This announcement actually includes two noteworthy topics: GaN and Python.

Angelov-GaN is an industry-standard compact device model for GaN semiconductor devices. Since GaN devices typically operate at high power, it is important to be able to model thermal issues and their impacts on device characteristics. Designers working with GaN quickly realized that GaAs models were not good enough. Fortunately, Prof. I. Angelov at Chalmers University of Technology developed his Angelov-GaN model as an alternative.

In its IC-CAP 2013.01, Agilent has fully embraced the Angelov model with the W8533 Angelov-GaN extraction package. An interface lets users execute a step-by-step extraction flow to obtain model parameters. A turnkey flow aims to provide a quick-start modeling of GaN devices. Roberto Tinti, device modeling product manager with Agilent EEsof EDA explained that the company developed the extraction package in conjunction with some Japanese and US GaN partners, but he was unable to reveal company names.

read more from the original...

ASP-DAC 2013 CALL FOR PARTICIPATION

Asia and South Pacific Design Automation Conference 2013

Pacifico Yokohama, Yokohama, JAPAN

January 22 - 25, 2013

http://www.aspdac.com/aspdac2013

WEB REGISTRATION DUE!!!: *** Jan. 17, 2013 ***

Please check the Registration Page:

http://www.aspdac.com/aspdac2013/registration/

For technical program, Please check the following link:

http://www2.infonets.hiroshima-u.ac.jp/aspdac/program/

---

ASP-DAC 2013 is the eighteenth in a series of annual international conference on VLSI design automation. Asia and South Pacific region is one of the most active regions of design and fabrication of silicon chips in the world. The conference aims are providing the Asian and South Pacific CAD/DA and Design community with opportunities of interchanging ideas and collaboratively discussing the directions of the technologies related to all of Electronic Design Automation (EDA).

---

I N D E X [1] Keynote Speeches
[2] Designers' Forum
[3] Special Sessions
[4] Technical Sessions
[5] Tutorial

---

[1] Keynote Speeches

---

We have three keynote speakers from industry.
Keynote I : Wednesday, January 23, 8:30-10:00
"From Circuits to Cancer"
Dr. Sani Nassif, IBM
Keynote II : Thursday, January 24, 9:00-10:00
"Gearing Up for the Upcoming Technology Nodes"
Dr. Kee Sup Kim, Samsung Electronics
Keynote III : Friday, January 25, 9:00-10:00
"Human, Vehicle and Social Infrastructure System Development for
Sustainable Mobility - Development Innovation based on Large-Scale
Simulation -"
Dr. Hiroyuki Watanabe, Toyota Motor Corp.

---

[2] Designers' Forum

---

Designers' Forum is conceived as a unique program that shares the design experience and solutions of real product developments among LSI designers and EDA academia/developers. Admission fee is included in the Conference registration fee. Registration for Designers' Forum only is also available.

5A January 24, 13:40-15:40
Invited Talks: "Heterogeneous Devices and Multi-Dimensional Integration Design Technologies"
(Sony, Tokyo Inst. of Tech., TSMC, STARC, IMEC)
6A January 24, 16:00-18:00
Panel Discussion: "Future Direction and Trend of Embedded GPU"
(Panasonic, Kyushu Univ., ARM, Intel, Digital Media Professionals,
Fujitsu Lab.)
8A January 25, 13:40-15:40
Invited Talks: "Photonics for Embedded Systems"
(Hitachi, Luxtera, NEC, PETRA)
9A January 25, 16:00-18:00
Panel Discussion: "Harmonized Hardware-Software Co-design and Co-verification"
(STARC, Fujitsu Lab., Renesas, Tokyo Inst. of Tech., RWTH Aachen Cadence, Synopsys)

---

[3] Special Sessions

---

1D January 23, 10:20-12:20
University LSI Design Contest (Presentation + Poster Discussion)
21 designs are selected from 36 designs from five countries/areas.
1A January 23, 10:20-12:20
Invited Talks: "Advanced Modeling and Simulation Techniques for
Power/Signal Integrity in 3D Design"
(San Diego State Univ., Shizuoka Univ., KAIST, National Taiwan Univ.)
2A January 23, 13:40-15:40
Invited Talks: "Dependability of on-Chip Systems"
(Karlsruhe Inst. of Tech., Kyoto Univ., UC Irvine, UCLA)
3A January 23, 16:00-18:00
Invited Talks: "Design Automation for Flow-Based Microfluidic Biochips: Connecting Biochemistry to Electronic Design Automation"
(Ritsumeikan Univ., National Cheng Kung Univ., NAIST,
Tech. Univ. of Denmark, UC Riverside)
4A January 24, 10:20-12:20
Invited Talks: "High-Level Synthesis and Parallel Programming Models for FPGAs"
(Altera Toronto Technology Center, Advanced Digital Sciences Center,
Univ. of Illinois, Urbana-Champaign)
4D January 24, 10:20-12:20
Invited Talks: "Emerging Security Topics in Electronic Designs and Mobile Devices"
(Air Force Research Lab., New York Univ., UCLA, Univ. of Pittsburgh, Rutgers Univ.)
7A January 25, 10:20-12:20
Invited Talks: "Many-Core Architecture and Software Technology"
(Kyushu Univ., Univ. of Electro-Communications, Ritsumeikan Univ.,
Fixstars Corp., Fixstars Multicore Lab., TOPS Systems Corp.)

---

[4] Technical Sessions

---

97 papers are selected from 311 submissions for regular presentation
that cover key topics from system design to physical design. For
more details, please see the Home page:
http://www.aspdac.com/aspdac2013/technical_program/

---

[5] Tutorial

---

On January 22, five two-hour tutorials are scheduled, which will provide the audience with an introduction to hot topics in Embedded Multicore Programming, Pulse Based Design, Non-volatile System, Dependable Embedded Systems and RF-MEMs. Each tutorial will be presented twice a day to allow attendees to cover multiple topics. If you register for tutorials, you have the option to select three out of the five topics. Access to electronic files of tutorial presentations and a lunch coupon is included in Tutorial fee.

Tutorial-1 January 22, 9:30 - 11:30, 13:00 - 15:00
Programming Embedded Multiprocessor Systems: Application Code Mapping
and Performance Estimation Technologies
Tutorial-2 January 22, 9:30 - 11:30, 15:30 - 17:30
Pulse Based Design and Optimization
Tutorial-3 January 22, 13:00 - 15:00, 15:30 - 17:30
Temperature- and Process Variation-Aware Dependable Embedded Systems
Tutorial-4 January 22, 9:30 - 11:30, 13:00 - 15:00
Non-Volatile Memory Based Design
Tutorial-5 January 22, 13:00 - 15:00, 15:30 - 17:30
Introduction to RF CMOS and MEMS Design

---

Home page: http://www.aspdac.com

---

Sponsored by: ACM SIGDA, IEEE CASS, IEICE ESS, IPSJ SIGSLDM
Technical co-sponsor: IEEE CEDA

---

Japan Electronics Show Association（JESA）
1-1-3, Otemachi, Chiyoda-ku, Tokyo, 100-0004, Japan
Tel: 81-3-6212-5231 Fax: 81-3-6212-5225
E-mail: aspdac2013@aspdac.com

10th IWCM Workshop Program

10th International Workshop on Compact Modeling 

January 22 (Tue), 2013 

Pacifico Yokohama, Room 419

Yokohama, Japan

Time	#	Title	Authors	Affiliation
9:00-9:10		Opening: H. J.  Mattausch (Workshop Chair)
		Power Devices   Chair: D. Navarro
9:10-9:30	1	HiSIM_HV Temperature Modeling for Multi-Geometry LDMOS: Comparison of the Temperature Flag Options	Y. Iino	Silvaco Japan
9:30-9:50	2	Analysis and Further Improvements of the Drain-Resistance Modeling in HiSIM_HV	T. Umeda et al.	Hiroshima University
9:50-10:10	3	Floating-Base Effect Modeling for IGBT Structure using Potential Modification	T. Yamamoto et al.	Denso
10:10-10:30		- Break -
		Novel FET Structures Chair: T. Nakagawa
10:30-10:50	4	Study on Dynamic Threshold Nanowire Tunnel FET	A. Zhang et al.	Peking University Shenzhen
10:50-11:10	5	A DC Model of TFETs for SPICE Simulations	L. Zhang and M. Chan	HK UST
11:10-11:30	6	A Surface Potential Based Compact Model of Organic Thin-Film Transistor for Circuit Simulation	T.K. Maiti et al.	Hiroshima University
11:30-11:40		-  Break -
		Optical and Wireless Chair: J. He
11:40-12:00	7	An Embedded Modulation of Silicon Germanium FIN-LED - A simulation study	J. Kwon et al.	Seoul National University
12:00-12:20	8	Predicting Key Parameters of Inductive Power Links	S. Raju et al.	HK UST
12:20-14:00		- Lunch Break -
		Aging and Degradation Chair: M. Miura-Mattausch
14:00-14:40	9	Invited Keynote: Interaction of Bloch Carrier and Bound State in the Reliability Modeling	Y.J. Park and S. Choi	Seoul National University
14:40-15:00	10	Development of Unified Predictive NBTI Model and its Application for Circuit Aging Simulation	C. Ma et al.	Hiroshima University, STARC
15:00-15:20	11	Effects of Nonlocal Concentration of Carriers in the Oxide for NBTI Simulation	S. Rhee et al.	Seoul National University
15:20-15:40		-  Break -
		Fabrication Variation Chair: Y. J. Park
15:40-16:00	12	Parameter Extraction for Statistical Variation of HV-MOSFETs	Y. Ueda et al.	Ricoh, STARC
16:00-16:20	13	Analysis of Gate-Length Dependence of MOSFET Random Variation by Using HiSIM-RP	S. Kumashiro et al.	Renesas Electronics
16:20-16:40	14	Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance	Y. Zhu et al.	Peking University Shenzhen
16:40-16:50		Closing: H.J. Mattausch (Workshop Chair)

IDESA Lecture

Lecture: MOSFET Modelling
J-M. Sallese; EPFL

Specific 90nm physical effects (DIBL, gate current, mobility saturation, velocity saturation). Available models and their RF performance: BSIM, EKV3, PSP. Modeling of analog and RF parameters (e.g., gm/ID, gm/gDS, CV modeling, gate leakage, etc.). Other topics include: noise modeling, distortion, breakdown effects, thermal issues and power devices, and physical layout effects (parasitics, test, maximizing gain-bandwidth, etc.). 

Location: STFC/RAL, UK; From: 14-Jan-2013 To: 18-Jan-2013

[more about IDESA Courses]

Job offer for Compact Modelling Engineer.

A job offer for compact modelling engineers, found in the web. For more information about the company, visit their website. Remember that we're not associated with them in any manner, and that we only post this as an information.

Compact Model Engineer
Reporting To: VP of Technology
Company: IO Semiconductor, Inc.
Location: San Diego, CA

Job Description and Responsibilities

• Collaborate with product development, technology development and process engineering teams on the evaluation, optimization, validation, assessment and characterization of compact device models for circuit simulation.
• Characterization and analysis of solid-state devices
• Refinement and optimization of compact models for improved analog and RF
• design efficiency and implementation on EDA platforms
• DC and RF Spice model parameter sets for typical and skewed conditions
• Device and circuit simulations
• Test structure designs for parameter extractionReports, presentations and interpretations of simulation and characterization results

Required Skills and Experience

• MS or PhD in electrical engineering, physics or equivalent
• Solid technical understanding of semiconductor device physics, device
• characterization and compact modelling for circuit simulation.
• Experience with electrical characterization, including proficiency in setting-up
• and programming measurement systems.
• Programming experience in at least one high-level, script-based language, such as
• HP Basic, Matlab or LabVIEW.
• Experience in test structure design and layout.
• Expertise in silicon-on-insulator (SOI) transistor physics and high speed device
• characterization are highly desirable.
• Experience with process and device simulation and modelling (TCAD) tools is
• desirable.
• Excellent verbal and written communication skills and a proven ability to work in
• teams.
• Excellent analytical skills
• Excellent time management and organisational skills
• A strong, hands-on individual contributor and a self-starter
• Sound communication and interpersonal skills
• Demonstrated ability to work effectively with others