Wednesday, January 30, 2013

Why- and how- to integrate Verilog-A compact models in SPICE simulators

Article first published online: 20 JUL 2012
by Maria-Anna Chalkiadaki1, Cédric Valla2, Frédéric Poullet2 and Matthias Bucher1 (1. Department of Electronic and Computer Engineering, Technical University of Crete, 73100 Chania, Greece and 2. Dolphin Integration, 38242 Meylan, France)
SUMMARY: This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models’ Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models.

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