The 2008 IEEE International Electron Devices Meeting (IEDM) will be held in the Hilton San Francisco Hotel in San Francisco, CA, from December 15 to 17 2008.
IEDM is the top conference in the field of electron devices. It is of course the most competitive one. Only truly outstanding papers are accepted. It is highly recommended that experimental results are shown, also some good simulation papers can be also accepted.
Two short courses will be held on Sunday, december 14: 22 nm Technology and More than Moore: Technologies for Functional Diversification.
This year there will also be plenary presentations by Peter Fromherz of Max Planck Institute; Tatsuo Saga from Sharp; Stefan K. Lai from Ovonyx, Inc.
Deadline for abstract submissions is June 27 2008 at 5.00 pm Pacific Standard Time.
Topics include all aspects related to electron devices, grouped in several areas:
-CMOS DEVICES & TECHNOLOGY (CDT)
-CHARACTERIZATION, RELIABILITY and YIELD (CRY)
-DISPLAYS, SENSORS, AND MEMS (DSM)
-MEMORY TECHNOLOGY (MT)
-MODELING AND SIMULATION (MS)
-PROCESS TECHNOLOGY (PT)
-QUANTUM, POWER, AND COMPOUND SEMICONDUCTOR DEVICES (QPC)
-SOLID STATE AND NANOELECTRONIC DEVICES (SSN)
This year the area of Modeling and Simulation (MS) explicitly includes "physical and compact models for devices and interconnects". And it is said "Submissions should advance the art of modeling and simulation or apply existing techniques to gain new insights into devices".
If you have important results to show, I vively recommend to send an abstract to IEDM. It is the best place to present them, and to discuss them with the top people. Even if your abstract is rejected, or if you do not have any new results to show, I encourage researchers to attend IEDM, including compact modeling researchers.
May 28, 2008
May 23, 2008
OSC'08
The 2008 Organic Semiconductor Conference (OSC-08) will take place in Frankfort (Germany), from September 28 to October 1 2008. The conference will be held in the Congress Centre, at the Frankfort Messe.
OSC-08 includes three tracks with presentations by invited speakers plus one track with peer review papers, a poster session, and also an exhibition of leading organic semiconductor technology companies, as well as an exhibitor forum.
Topics include all aspects related to development, manufacturing and investment in organic semiconductor technologies and organic electronics. Besides, this year, for the first time OSC-08 will also cover carbon nanotubes, graphenes and fullerenes.
The deadline for review paper submission is May 25 2008.
The invited speakers come from both academia and industry. Among them, there are very prestigious researchers such as Hagen Klauk (Max Planck Institute for Solid State Research), Karlheinz Bock (Fraunhofer IZM), Takao Someya (University of Tokyo), Edzer Huitema (Polymer Vision), or Jan Genoe (IMEC).
OSC-08 includes three tracks with presentations by invited speakers plus one track with peer review papers, a poster session, and also an exhibition of leading organic semiconductor technology companies, as well as an exhibitor forum.
Topics include all aspects related to development, manufacturing and investment in organic semiconductor technologies and organic electronics. Besides, this year, for the first time OSC-08 will also cover carbon nanotubes, graphenes and fullerenes.
The deadline for review paper submission is May 25 2008.
The invited speakers come from both academia and industry. Among them, there are very prestigious researchers such as Hagen Klauk (Max Planck Institute for Solid State Research), Karlheinz Bock (Fraunhofer IZM), Takao Someya (University of Tokyo), Edzer Huitema (Polymer Vision), or Jan Genoe (IMEC).
May 7, 2008
Papers on Volume 52, Issue 6, of Solid-State Electronics
Some new papers on the Volume 52, Issue 6, Pages 839-996 (June 2008) of Solid-State Electronics.
A universal electron mobility model of strained Si MOSFETs based on variational wave functions
Renrong Liang, Debin Li and Jun Xu
Substrate current characterization and optimization of high voltage LDMOS transistors
Jun Wang, Rui Li, Yemin Dong, Xin Zou, Li Shao and W.T. Shiau
Small-signal performance and modeling of sub-50 nm nMOSFETs with fT above 460-GHz
V. Dimitrov, J.B. Heng, K. Timp, O. Dimauro, R. Chan, M. Hafez, J. Feng, T. Sorsch, W. Mansfield, J. Miner, A. Kornblit, F. Klemens, J. Bower, R. Cirelli, E.J. Ferry, A. Taylor, M. Feng and G. Timp
Modeling of strained CMOS on disposable SiGe dots: Shape impacts on electrical/thermal characteristics
Sébastien Frégonèse, Yan Zhuang and Joachim N. Burghartz
A physical model of floating body effects in polysilicon thin film transistors
W.J. Wu, R.H. Yao, T. Chen, R.S. Chen, W.L. Deng and X.R. Zheng
Enjoy your reading!
A universal electron mobility model of strained Si MOSFETs based on variational wave functions
Renrong Liang, Debin Li and Jun Xu
Substrate current characterization and optimization of high voltage LDMOS transistors
Jun Wang, Rui Li, Yemin Dong, Xin Zou, Li Shao and W.T. Shiau
Small-signal performance and modeling of sub-50 nm nMOSFETs with fT above 460-GHz
V. Dimitrov, J.B. Heng, K. Timp, O. Dimauro, R. Chan, M. Hafez, J. Feng, T. Sorsch, W. Mansfield, J. Miner, A. Kornblit, F. Klemens, J. Bower, R. Cirelli, E.J. Ferry, A. Taylor, M. Feng and G. Timp
Modeling of strained CMOS on disposable SiGe dots: Shape impacts on electrical/thermal characteristics
Sébastien Frégonèse, Yan Zhuang and Joachim N. Burghartz
A physical model of floating body effects in polysilicon thin film transistors
W.J. Wu, R.H. Yao, T. Chen, R.S. Chen, W.L. Deng and X.R. Zheng
Enjoy your reading!
May 6, 2008
Synopsys Launches HSPICE Integrator Program With 25 Founding Members
It seems that Synopsys is trying to get back the leading position in the simulators market. Have a look at the post in their news section (disregard the self-publicity they do... it's natural in a company...). I copy here the post, because the final destination of a compact model is to be implemented... and one has to know which are the leading tools...
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today launched its HSPICE® Integrator Program to further promote integration between Synopsys' HSPICE simulation solution and other electronic design automation (EDA) products. The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
Founding members of the HSPICE Integrator Program include: Accelicon Technologies Inc., Agilent EEsof EDA, Altos Design Automation, Inc., Apache Design Solutions, Applied Simulation Technology, ATEEDA, AWR, Computer Simulation Technology (CST), Helic S.A., Interra Systems Inc., Jedat Inc., Mephisto Design Automation (MDA), MunEDA GmbH, Nangate Inc., Novas Software, OEA International, Inc., Orora Design Technologies, Inc., Physware, Inc., ProPlus Design Solutions, Inc., Signal Integrity Software, Inc. (SiSoft), Sigrity, Inc., Silicon Canvas, Solido Design Automation Inc., Veritools Inc., and Z Circuit Automation. For more information, visit the HSPICE Integrator Program, http://www.synopsys.com/hspice_integrator/
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today launched its HSPICE® Integrator Program to further promote integration between Synopsys' HSPICE simulation solution and other electronic design automation (EDA) products. The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
Founding members of the HSPICE Integrator Program include: Accelicon Technologies Inc., Agilent EEsof EDA, Altos Design Automation, Inc., Apache Design Solutions, Applied Simulation Technology, ATEEDA, AWR, Computer Simulation Technology (CST), Helic S.A., Interra Systems Inc., Jedat Inc., Mephisto Design Automation (MDA), MunEDA GmbH, Nangate Inc., Novas Software, OEA International, Inc., Orora Design Technologies, Inc., Physware, Inc., ProPlus Design Solutions, Inc., Signal Integrity Software, Inc. (SiSoft), Sigrity, Inc., Silicon Canvas, Solido Design Automation Inc., Veritools Inc., and Z Circuit Automation. For more information, visit the HSPICE Integrator Program, http://www.synopsys.com/hspice_integrator/
May 5, 2008
Memristor
A friend of us (Francisco J. Garcia) has pointed out a recent paper in Nature Letters (Vol 453| 1 May 2008| doi:10.1038/nature06932). I post here the abstract, because it is very interesting, though not very related to compact modeling:
Authors: Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart & R. Stanley Williams
ABSTRACT: Anyone who ever took an electronics laboratory class will be familiar with the fundamental passive circuit elements: the resistor, the capacitor and the inductor. However, in 1971 Leon Chua reasoned from symmetry arguments that there should be a fourth fundamental element, which he called a memristor (short for memory resistor). Although he showed that such an element has many interesting and valuable circuit properties, until now no one has presented either a useful physical model or an example of a memristor.
Here we show, using a simple analytical example, that memristance arises naturally in nanoscale systems in which solid-state electronic and ionic transport are coupled under an external bias voltage. These results serve as the foundation for understanding a wide range of hysteretic current–voltage behaviour observed in many nanoscale electronic devices2–19 that involve the motion of charged atomic or molecular species, in particular certain titanium dioxide cross-point switches20–22.
There is a remarks to be done, following Francisco, since you can find a patent of a very similar device:
Genrikh et al
US Patent Application Publication No. US 2007/0200158 A1, Aug. 30, 2007
ELECTRODE STRUCTURE HAVING AT LEAST TWO OXIDE LAYERS AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME
Assignee: Samsung Electronics, Co., Ltd.
Filed: Jan. 19, 2007
Authors: Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart & R. Stanley Williams
ABSTRACT: Anyone who ever took an electronics laboratory class will be familiar with the fundamental passive circuit elements: the resistor, the capacitor and the inductor. However, in 1971 Leon Chua reasoned from symmetry arguments that there should be a fourth fundamental element, which he called a memristor (short for memory resistor). Although he showed that such an element has many interesting and valuable circuit properties, until now no one has presented either a useful physical model or an example of a memristor.
Here we show, using a simple analytical example, that memristance arises naturally in nanoscale systems in which solid-state electronic and ionic transport are coupled under an external bias voltage. These results serve as the foundation for understanding a wide range of hysteretic current–voltage behaviour observed in many nanoscale electronic devices2–19 that involve the motion of charged atomic or molecular species, in particular certain titanium dioxide cross-point switches20–22.
There is a remarks to be done, following Francisco, since you can find a patent of a very similar device:
Genrikh et al
US Patent Application Publication No. US 2007/0200158 A1, Aug. 30, 2007
ELECTRODE STRUCTURE HAVING AT LEAST TWO OXIDE LAYERS AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME
Assignee: Samsung Electronics, Co., Ltd.
Filed: Jan. 19, 2007
Apr 30, 2008
Process for the Selection of the Next Generation SOI MOSFET Compact Models
The Compact Modeling Council (CMC) has started the Process for the Selection of the Next Generation SOI MOSFET Compact Models.
The CMC is soliciting SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.
The deadline for candidate submission is May 5 2008. CMC officers will invite a number of selected model developers to the CMC Meeting in Boston, MA on 6/5/2008.
A new selection will be done after CMC members have had time to review the presentations given by model developers.
A SOI MOSFET model recommended by CMC will make lots of money!
Who wants to compete?
The CMC is soliciting SOI models for both partially-depleted (PD) and dynamic depletion (DD) applications. DD refers to SOI devices which exhibit PD behavior forsome bias regions, but are fully-depleted (FD) for others.
The deadline for candidate submission is May 5 2008. CMC officers will invite a number of selected model developers to the CMC Meeting in Boston, MA on 6/5/2008.
A new selection will be done after CMC members have had time to review the presentations given by model developers.
A SOI MOSFET model recommended by CMC will make lots of money!
Who wants to compete?
Training Course on SOI for analog,digital and RF SOCs and microsystems applications
This training course on SOI for analog,digital and RF SOCs and microsystems applications will take place at IMEC (Heverlee, Belgium) on May 15-16 2008.
This course is organized by the IMEC Training Center in collaboration with Prof. Denis Flandre (UCL, Louvain-la-Neuve, Belgium).
The course will address topics such as SOI MOSFET specific behaviors and performance assessments, SOI MOS analog design, micromachined SOI MEMS, on-wafer wideband characterization, and SOI FinFET integration and circuits.
The lecturers are prestigeous researchers from IMEC and UCL, all of them experts in SOI technologies.
It seems a very interesting course for SOI MOS circuit designers!
This course is organized by the IMEC Training Center in collaboration with Prof. Denis Flandre (UCL, Louvain-la-Neuve, Belgium).
The course will address topics such as SOI MOSFET specific behaviors and performance assessments, SOI MOS analog design, micromachined SOI MEMS, on-wafer wideband characterization, and SOI FinFET integration and circuits.
The lecturers are prestigeous researchers from IMEC and UCL, all of them experts in SOI technologies.
It seems a very interesting course for SOI MOS circuit designers!
Course: "New Trends in Nanoelectronics" in Lausanne
The course "New Trends in Nanoelectronics" will be organized by Prof. Adrian M. Ionescu, from EPFL (Lausanne, Switzerland). This two-day course will take place in Lausanne on May 22-23 2008.
The purpose of the course is to provide a general knowledge about emerging nanoelectronics including technology, nanowires and nanotubes, memory device architectures, nanoelectromechanical devices, and benchmarking for circuit and system applications.
The lecturers that will participate will be A. M. Ionescu, K. E. Moselund (EPFL) and H. -S. Philip Wong (stanford University).
The purpose of the course is to provide a general knowledge about emerging nanoelectronics including technology, nanowires and nanotubes, memory device architectures, nanoelectromechanical devices, and benchmarking for circuit and system applications.
The lecturers that will participate will be A. M. Ionescu, K. E. Moselund (EPFL) and H. -S. Philip Wong (stanford University).
Apr 29, 2008
Open Ph D Student position in nanoelectronic device modeling
We offer one fellowship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in
The duration of the grant will be at least three years, possibly four. The monthly salary will be 1000 Euro/month.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.
The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel nanoscale semiconductor devices. It will be related to two European projects in which the hosting group participates.
To get more information about our areas of research in the DEEEA, you can visit the website:
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos/scholarships.htm
And
http://sauron.etse.urv.es/DEEEA/angles/recerca/nephos
Required documents for applicants
Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible)
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours of each subject). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates can send their documents by e-mail, but in fact we will need original and copy documents (or authenticated copy) of them; therefore we suggest to send the documents by postal mail.
Applications should be sent to:
Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
43007
Email: benjamin.iniguez@urv.cat
Tel: +34977558521 Fax:+34977559610
Deadline:
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@urv.cat) for more information
Apr 21, 2008
MIGAS'08 Summer School
The 11 session of the MIGAS Summer School (International Summer School on Advanced Microelectronics) will be dedicated to Nanoscale CMOS and Si-Based Beyond CMOS Nanodevices.
MIGAS 2008 will take place in Autrans (French Alps) from June 28 to July 4 2008.
MIGAS is addressed to PhD students, engineers and researchers coming both from the university and from industry of the semiconductors.
The attendees will be able to improve their knowledge on nanoelectronic devices by means a set of lectures conducted by top international scientists.
The scienfific programme will consists of the following lectures:
Besides, MIGAS includes a great social programme, with activities such as excursions the day before the beginning of the school, wine tastings, and copious dinners based on the excellent Dauphinoise and Vercors cuisine, and with great wines. Of course, the area around Autrans offers excellent opportunities for hiking, mountaineering, mountain-biking, lake swimming and more.
Registration includes accomodation in the resort as well as all meals.
MIGAS 2008 will take place in Autrans (French Alps) from June 28 to July 4 2008.
MIGAS is addressed to PhD students, engineers and researchers coming both from the university and from industry of the semiconductors.
The attendees will be able to improve their knowledge on nanoelectronic devices by means a set of lectures conducted by top international scientists.
The scienfific programme will consists of the following lectures:
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Registration includes accomodation in the resort as well as all meals.
Apr 18, 2008
TFT Symposium in the ECS Meeting in Hawaii
The 214th Electrochemical Society (ECS) Meeting will be held in Honolulu, Hawaii, on October 12-17 2008, in the Hilton Hawaiian Village.
The ECS Meeting includes a number of Symposia.
For the TFT community, I want to highlight the TFT 10 Symposium.
The TFT symposium is an intersting forum for the presentation and discussion of
the latest developments in all types of thin film transistors (TFTs) and
related fields. This symposium is chaired by Prof Yue Kuo (Texas A&M University)
Papers can deal with all aspects of fabrication processes, materials, device
physics, characterization, structures, and applications of TFTs. This TFT symposium will address the following topics:
(1.) new TFT Structures; (2.) novel or new processes; (3.) organic, inorganic, oxide, etc. thin film materials; (4.) device physics, modeling, characterization, and reliability; (5.) applications in LCDs, imagers, sensors, biochips, MEMS, etc.; (6.) applications in circuits; and (7.) integration of TFTsto large area displays, VLSIC, and other complex systems.
Abstracts should be submitted electronically to ECS headquarters by May 30.
Being this TFT Symposium in Hawaii, no doubt it will be a big success!
The ECS Meeting includes a number of Symposia.
For the TFT community, I want to highlight the TFT 10 Symposium.
The TFT symposium is an intersting forum for the presentation and discussion of
the latest developments in all types of thin film transistors (TFTs) and
related fields. This symposium is chaired by Prof Yue Kuo (Texas A&M University)
Papers can deal with all aspects of fabrication processes, materials, device
physics, characterization, structures, and applications of TFTs. This TFT symposium will address the following topics:
(1.) new TFT Structures; (2.) novel or new processes; (3.) organic, inorganic, oxide, etc. thin film materials; (4.) device physics, modeling, characterization, and reliability; (5.) applications in LCDs, imagers, sensors, biochips, MEMS, etc.; (6.) applications in circuits; and (7.) integration of TFTsto large area displays, VLSIC, and other complex systems.
Abstracts should be submitted electronically to ECS headquarters by May 30.
Being this TFT Symposium in Hawaii, no doubt it will be a big success!
SINANO Device Modeling Summer School
The Third SINANO Device Modeling Summer School will be held in the historic Bertinoro Castle (Bertinoro (FC), Italy) on September 1-5 2008.
The SINANO Summer School was held in 2005 and 2006 in the framework of the former SINANO European Network of Excellence, and is currently continued under the umbrella of the new NANOSIL Network of Excellence and of the Integrated Project PULLNANO.
The goal of the SINANO Summer School is to increase the knowledge of PhD students and postdoctoral researchers in the fields of advanced modeling, simulation and characterization techniques for conventional and nanoscale CMOS devices. The lectures use to address topics such as device physics, device models, numerical techniques, device simulation tools, and experimental characterization techniques.
Regarding the topic of "Analytical and compact models", Dr Raphaël Clerc (IMEP, France), will talk about “Device technology oriented analytical models”
Peter Baumgartner (Infineon) will give a lecture entitled: “RF and noise characterization of transistors and circuits”
Prof Paolo Pavan will talk about “Current trends in non-volatile memories”
Besides, there will also be a great social program which will include dinners, hiking and other outdoor activities..
The registration form should be sent before July 30.
The SINANO Summer School was held in 2005 and 2006 in the framework of the former SINANO European Network of Excellence, and is currently continued under the umbrella of the new NANOSIL Network of Excellence and of the Integrated Project PULLNANO.
The goal of the SINANO Summer School is to increase the knowledge of PhD students and postdoctoral researchers in the fields of advanced modeling, simulation and characterization techniques for conventional and nanoscale CMOS devices. The lectures use to address topics such as device physics, device models, numerical techniques, device simulation tools, and experimental characterization techniques.
The 5 days program of the School will be dedicated to the following topics:
Prospects for further development of CMOS technology
Transport models for device simulation
Experimental electrical device characterization
Analytical and compact models
Post CMOS devices
Silicon technology for photo-voltaic energy conversion
Regarding the topic of "Analytical and compact models", Dr Raphaël Clerc (IMEP, France), will talk about “Device technology oriented analytical models”
Peter Baumgartner (Infineon) will give a lecture entitled: “RF and noise characterization of transistors and circuits”
Prof Paolo Pavan will talk about “Current trends in non-volatile memories”
Besides, there will also be a great social program which will include dinners, hiking and other outdoor activities..
The registration form should be sent before July 30.
Apr 15, 2008
Article in EDN: Modeling gaps in state-of-the-art mixed-signal SOC design
I've recently found an old (2006) paper on the EDN: Electronics Design, Strategy, News website. (I cannot reproduce it here because of the copyrights).
They discuss a bit about standardization efforts on Compact Modeling, and the different aspects that must be taken into account. I think it is a nice paper, even though it is slightly biased towards BSIM (only a bit: PSP, EKV and HiSIM are also mentioned... but not so extensively....).
They discuss a bit about standardization efforts on Compact Modeling, and the different aspects that must be taken into account. I think it is a nice paper, even though it is slightly biased towards BSIM (only a bit: PSP, EKV and HiSIM are also mentioned... but not so extensively....).
Papers in Volume 52, Issue 5, Pages 597-838 (May 2008) of Solid-State Electronics
It seems that this month's harvest has been quite good. There are some quite interesting papers
Low-frequency noise properties of double channel AlGaN/GaN HEMTs
S.K. Jha, C. Surya, K.J. Chen, K.M. Lau and E. Jelencovic
A fully 2-dimensional, quantum mechanical calculation of short-channel and drain induced barrier lowering effects in HEMTs
G. Krokidis, J.P. Xanthakis and N.K. Uzunoglu
Subthreshold characteristics of polysilicon TFTs
Wanling Deng, Xueren Zheng, Rongsheng Chen and Yuan Liu
Physics-based 1/f noise model for MOSFETs with nitrided high-κ gate dielectrics
Tanvir Hasan Morshed, Siva Prasad Devireddy, Zeynep Çelik-Butler, Ajit Shanware, Keith Green, J.J. Chambers, M.R. Visokay and Luigi Colombo
Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors
Abhay Deshpande and R.P. Jinda
Mobility model for compact device modeling of OTFTs made with different materials
M. Estrada, I. Mejía, A. Cerdeira, J. Pallares, L.F. Marsal and B. Iñiguez
Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs
Sung Jun Jang, Dae Hyun Ka, Chong Gun Yu, Won-Ju Cho and Jong Tae Park
Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs
A. Cerdeira, O. Moldovan, B. Iñiguez and M. Estrada
Low-frequency noise properties of double channel AlGaN/GaN HEMTs
S.K. Jha, C. Surya, K.J. Chen, K.M. Lau and E. Jelencovic
A fully 2-dimensional, quantum mechanical calculation of short-channel and drain induced barrier lowering effects in HEMTs
G. Krokidis, J.P. Xanthakis and N.K. Uzunoglu
Subthreshold characteristics of polysilicon TFTs
Wanling Deng, Xueren Zheng, Rongsheng Chen and Yuan Liu
Physics-based 1/f noise model for MOSFETs with nitrided high-κ gate dielectrics
Tanvir Hasan Morshed, Siva Prasad Devireddy, Zeynep Çelik-Butler, Ajit Shanware, Keith Green, J.J. Chambers, M.R. Visokay and Luigi Colombo
Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors
Abhay Deshpande and R.P. Jinda
Mobility model for compact device modeling of OTFTs made with different materials
M. Estrada, I. Mejía, A. Cerdeira, J. Pallares, L.F. Marsal and B. Iñiguez
Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs
Sung Jun Jang, Dae Hyun Ka, Chong Gun Yu, Won-Ju Cho and Jong Tae Park
Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs
A. Cerdeira, O. Moldovan, B. Iñiguez and M. Estrada
Apr 14, 2008
MOS-AK
I copy a mail from Wladek Grabinski:
The MOS-AK Eindhoven Workshop's presentations are available on-line
please visit: www.mos-ak.org/eindhoven
I would like to take this opportunity and thank all speakers and presenters for
their valuable contribution to the MOS-AK Meeting at MiPlaza. Selected MOS-AK
publications are recommended for further publications: www.mos-ak.org/eindhoven
Let me also acknowledge the workshop sponsors (MiPlaza, Agilent and Cascade) for
their generous financial support as well as local meeting organizers for their
support, smooth organization and perfect logistic of our modeling event. Such
events are unique platform for continuous promotion of local, European compact
modeling activities.
You are more than welcome to attend and contribute to coming modeling events:
* WCM'08 Workshop June 1-5, 2008, Boston, Massachusetts
* MIXDES'08 June 19-21, 2008 Poznan www.mixdes.org/Special_sessions.htm
* MOS-AK/ESSDERC/ESSCIRC Workshop September 19, 2008 www.mos-ak.org/edinburgh/
Mar 19, 2008
An interesting paper
Have a look, and share (if you wish) your comments...
Charge transport in boron-doped nano MOSFETs: Towards single-dopant electronics
Applied Surface Science, In Press, Accepted Manuscript, Available online 12 March 2008
Y. Ono, M.A.H. Khalafalla, K. Nishiguchi, K. Takashina, A. Fujiwara, S. Horiguchi, H. Inokawa and Y. Takahashi
Charge transport in boron-doped nano MOSFETs: Towards single-dopant electronics
Applied Surface Science, In Press, Accepted Manuscript, Available online 12 March 2008
Y. Ono, M.A.H. Khalafalla, K. Nishiguchi, K. Takashina, A. Fujiwara, S. Horiguchi, H. Inokawa and Y. Takahashi
Mar 18, 2008
IMEC reports methodology to analyze process variability compatible with DFM tools
It seems that, looking through the inherent self-publicity, the report (presented in DATE'08, by the way) is quite nice. I copy an excerpt here, but you can also access the full report in the original source.
Quoting Rudy Lauwereins, Vice President Nomadic Embedded Systems at IMEC:
"Up to now, most variability characterization work is done internally at IDMs on own technology and IP blocks. However, with the move to fabless and fablite companies, we want to bridge the gap between foundry and fabless companies on design-level impact of using most advanced semiconductor technologies. To this end, we invite IDMs, fabless system companies, fabless digital IP providers and foundries to collaborate within our Technology-Aware Design program to develop the necessary tools for designing reliable systems with variable and unreliable components. IMEC’s program is compatible with confidentiality constraints for high value proprietary IP blocks."
Quoting Rudy Lauwereins, Vice President Nomadic Embedded Systems at IMEC:
"Up to now, most variability characterization work is done internally at IDMs on own technology and IP blocks. However, with the move to fabless and fablite companies, we want to bridge the gap between foundry and fabless companies on design-level impact of using most advanced semiconductor technologies. To this end, we invite IDMs, fabless system companies, fabless digital IP providers and foundries to collaborate within our Technology-Aware Design program to develop the necessary tools for designing reliable systems with variable and unreliable components. IMEC’s program is compatible with confidentiality constraints for high value proprietary IP blocks."
Mar 17, 2008
Interesting papers on Applied Physics Letters
Some interesting papers, that appear in this month's issue ( Appl. Phys. Lett. 92, 2008):
Drift mobility and the frequency response of diode connected organic transistors, Brian Cobb, Yeon Taek Jeong, and Ananth Dodabalapur
Abstract
Effects of substrates on photocurrents from photosensitive polymer coated carbon nanotube networks, Yumeng Shi, Hosea Tantang, Chun Wei Lee, Cheng-Hui Weng, Xiaochen Dong, Lain-Jong Li, and Peng Chen
Abstract
Determining the interfacial density of states in metal-insulator-semiconductor devices based on poly(3-hexylthiophene), N. Alves and D. M. Taylor
Abstract
Carrier trapping and scattering in amorphous organic hole transporter, K. K. Tsung and S. K. So
Abstract
Drift mobility and the frequency response of diode connected organic transistors, Brian Cobb, Yeon Taek Jeong, and Ananth Dodabalapur
Abstract
Effects of substrates on photocurrents from photosensitive polymer coated carbon nanotube networks, Yumeng Shi, Hosea Tantang, Chun Wei Lee, Cheng-Hui Weng, Xiaochen Dong, Lain-Jong Li, and Peng Chen
Abstract
Determining the interfacial density of states in metal-insulator-semiconductor devices based on poly(3-hexylthiophene), N. Alves and D. M. Taylor
Abstract
Carrier trapping and scattering in amorphous organic hole transporter, K. K. Tsung and S. K. So
Abstract
Mar 6, 2008
Talk in EPFL (Switzerland)
I've got a mail from EPFL, announcing the next meeting of the SSCS chapter of West-Switzerland. It is going to take place at EPFL, and you can see the exact room in the map, looking for room C0016. Moreover, there will be a talk from Xing Zhou. I copy the post here:
Title: New Challenges in MOS Compact Modeling for Future Generation CMOS
School of Electrical & Electronic Engineering
Nanyang Technological University
50 Nanyang Avenue,
Singapore 639798
Where: EPFL, Building CO, Room CO016 (http://plan.epfl.ch)
When: Tuesday, March 11, 2008, 17h00
Abstract: As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges to developing a compact model suitable for these new device structures and requires a paradigm shift in the core model structure. Conventional bulk-MOS models are based on four-terminal unipolar conduction in a doped channel with ideal symmetrical PN-junction source/drain contacts. In MG/NW MOSFETs, however, the device becomes three-terminal with undoped channel and possible bipolar conduction, and source/drain contacts become an integral part of intrinsic channel. Source/drain asymmetry, either intentional or unintentional, in a theoretically symmetric MOSFET also becomes important to capture in a compact model, which is nontrivial in a model that depends on terminal source/drain swapping at the circuit level. In this talk, after a brief review of the history of compact model development and various approaches, we discuss these new challenges and demonstrate solution methods based on the unified regional modeling (URM) approach.
Bio: Xing Zhou received the B.E. degree from Tsinghua University, Beijing, China, in 1983, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, NY, in 1987 and 1990, respectively. From 1990 to 1991, he was a research associate in the Department of Electrical Engineering, the University of Rochester, where he worked on hot-carrier injection phenomena in MOS devices, as well as development of CAD tools for mixed-signal circuit simulation. From 1992 to 1995, he was a research fellow in the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, where he worked on Monte Carlo and numerical modeling of semiconductor and optoelectronic devices as well as mixed-signal circuit modeling and simulation. He is currently a tenured associate professor in the same school at NTU, as well as program director and lab supervisor of the computational nanoelectronics group. His current research focuses on development of compact models for circuit simulation for conventional and emerging nanoscale MOS devices. In November and December of 1997 as well as in February and March 2001, he was a visiting fellow at the Center for Integrated Systems, Stanford University, California. In January 2003, he was a visiting professor at Hiroshima University, Japan. In May 2007, he was a visiting professor at Universiti Teknologi Malaysia. He is the founding chair of the Workshop on Compact Modeling (WCM) in association with the Nano Science and Technology Institute (NSTI) Nanotech Conference since 2002. He was the recipient of the 2006 NSTI Fellow award.
Dr. Zhou is an elected member of the IEEE Electron Devices Society (EDS) Administrative Committee, chair of the EDS Asia Pacific Subcommittee for Regions/Chapters, a member of the EDS Compact Modeling and VLSI Technology and Circuits technical committees as well as the Membership, Publications, and Educational Activities committees, and an EDS newsletter editor for Region 10 (Australia, New Zealand & South Asia). He has served as an EDS distinguished lecturer since 2000. Since 2007 Dr. Zhou is an editor of the IEEE Electron Device Letters.
Mar 3, 2008
Postdoc position on compact device modeling in Spain
As Professor in the Universitat Rovira i Virgili (Tarragona, Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry under the Programa Juan de la Cierva) related to the European projects we participate in: the NANOSIL Network of Excellence (a project about technology, characterization and modeling of Si nanodevices) and the Compact Modeling Network (of which I am the coordinator).
The candidate should be a person who holds a PhD as awarded within the three years prior to the date when the period for presentation of application forms closes. If the candidate does not hold a PhD yet, the deadline to be awarded a PhD is the date of publication of the Awarding Resolution in the Ministry of Education and Science web site.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the European projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects. In the case of NANOSIL Network of Excellence, the targeted devices are mostly: Schottky Barrier SOI MOSFETs, strained Si SOI MOSFETs, and Si Nanowires. In the case of the Compact Modeling Network the devices addressed are : multi-gate MOSFETs (FinFETs, DG MOSFETs,...), High Voltage MOSFETs and advanced HEMTs.
The postdoc position, which will be a contract, will have a duration of up to 3 years. The net salary will be around 1900 Euro/months. Researchers from many European countries will have tax exemption during the first two years, so they will be able to have much higher net salaries.
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: March 11 2008
MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat
Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.
About Tarragona:
The candidate should be a person who holds a PhD as awarded within the three years prior to the date when the period for presentation of application forms closes. If the candidate does not hold a PhD yet, the deadline to be awarded a PhD is the date of publication of the Awarding Resolution in the Ministry of Education and Science web site.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the European projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects. In the case of NANOSIL Network of Excellence, the targeted devices are mostly: Schottky Barrier SOI MOSFETs, strained Si SOI MOSFETs, and Si Nanowires. In the case of the Compact Modeling Network the devices addressed are : multi-gate MOSFETs (FinFETs, DG MOSFETs,...), High Voltage MOSFETs and advanced HEMTs.
The postdoc position, which will be a contract, will have a duration of up to 3 years. The net salary will be around 1900 Euro/months. Researchers from many European countries will have tax exemption during the first two years, so they will be able to have much higher net salaries.
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: March 11 2008
MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat
Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.
About Tarragona:
Tarragona is located on the Mediterranean, in the heart of the Costa Daurada, in the south of Catalonia, about 100 Km south from Barcelona. Tarragona is well connected to Barcelona by highway, and frequent trains and buses. It has also a direct bus connection with Barcelona Airport. Besides, it has high-speed rail connection with Madrid and Barcelona.
Tarraco (the Roman name for
Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: “The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring.” Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage,
Pre-doc position available
I've got an offer for a pre-doc position within the Electronic Technology Group of the Balearic Islands University. The amount of the bourse are around 1000 euros per month, for four years. After this time, the candidate should be able to read the PhD thesis, and obtain this degree.
Those interested, please contact Eugenio Garcia: eugeni.garcia(_at_)uib.es (substitute _at_ by @)
Those interested, please contact Eugenio Garcia: eugeni.garcia(_at_)uib.es (substitute _at_ by @)
New IC-CAP package
A new addition from Agilent to their unofficially official parameter extraction program. As they say:
"Creating device-simulation models for advanced process technologies is problematic because physical wafers that meet specifications with acceptable yield often are not produced for months to years," said Roberto Tinti, product marketing manager with Agilent's EEsof EDA division. "Our Target Modeling Package addresses this by providing an easy way to extract CMOS device models from a reduced set of Process Control Monitor data before wafers from a new process are produced. Our customers tell us that extracting simulation models before a process matures can save them several months in a typical design cycle."
You can have a look to the full press release here.
"Creating device-simulation models for advanced process technologies is problematic because physical wafers that meet specifications with acceptable yield often are not produced for months to years," said Roberto Tinti, product marketing manager with Agilent's EEsof EDA division. "Our Target Modeling Package addresses this by providing an easy way to extract CMOS device models from a reduced set of Process Control Monitor data before wafers from a new process are produced. Our customers tell us that extracting simulation models before a process matures can save them several months in a typical design cycle."
You can have a look to the full press release here.
Feb 29, 2008
Play a game
Applied Materials has launched a small game about how to made a 65nm transistor... It's quite interesting, and let's you know quite a lot about the fabrication process.... Have a look here, and see if you can get 100/100 score!
Feb 20, 2008
MIEL'08
The 26th International Conference on Microelectronics (MIEL 2008) will be held in Nis (Serbia) on May 11-14 2008.
MIEL is one of the most prestigeous Microelectronics conferences in Europe. Topics ofthe conference include all subjects related to electronic devices and electronic circuits.
This year a number of top researchers in electron devices will give invited presentations.
Prof Jamal Deen will present an invited contribution entitled "Towards Low-cost, High-Sensitivity, Integrated Biosensors".
Prof. Mark Lundstrom will give a very interesting invited talk, entitled: "Electronics from the Bottom Up: An Approach to 21st Century Electronic Devices"
And one invited presentation about compact modeling: Dr Slobodan Mijalkovic, another invited speaker, will make a presentation on compact modeling of organic transistors: "Modelling of Organic Field-Effect Transistors for Technology and Circuit Design"
Prof E.Sangiorgi will talk about "Silicon Based Nano-MOSFET: New Materials, New Device Architectures, and New Challenges for Device Simulation".
Prof.Mikael Östling will present new results about Schottky-Barrier MOSFETs: "Towards a Nano-MOSFET with Schottky Barrier Drain/Source"
And there is a very challenging invited presentation from Prof Radivoje Popovic: "Counting Single Electrons in CMOS Circuit"
There are many other invited presentations!
By the way, the social programme of MIEL is superb! Every evening there is a copious dinner, based on traditional and delicious Serbian cuisine. Besides, there is lot of slivovitz, fun and dancing in the gala dinner!
MIEL is one of the most prestigeous Microelectronics conferences in Europe. Topics ofthe conference include all subjects related to electronic devices and electronic circuits.
This year a number of top researchers in electron devices will give invited presentations.
Prof Jamal Deen will present an invited contribution entitled "Towards Low-cost, High-Sensitivity, Integrated Biosensors".
Prof. Mark Lundstrom will give a very interesting invited talk, entitled: "Electronics from the Bottom Up: An Approach to 21st Century Electronic Devices"
And one invited presentation about compact modeling: Dr Slobodan Mijalkovic, another invited speaker, will make a presentation on compact modeling of organic transistors: "Modelling of Organic Field-Effect Transistors for Technology and Circuit Design"
Prof E.Sangiorgi will talk about "Silicon Based Nano-MOSFET: New Materials, New Device Architectures, and New Challenges for Device Simulation".
Prof.Mikael Östling will present new results about Schottky-Barrier MOSFETs: "Towards a Nano-MOSFET with Schottky Barrier Drain/Source"
And there is a very challenging invited presentation from Prof Radivoje Popovic: "Counting Single Electrons in CMOS Circuit"
There are many other invited presentations!
By the way, the social programme of MIEL is superb! Every evening there is a copious dinner, based on traditional and delicious Serbian cuisine. Besides, there is lot of slivovitz, fun and dancing in the gala dinner!
Feb 13, 2008
2008 IEEE International SOI Conference
The 2008 IEEE International SOI Conference will be held 6 – 9 October, 2008 at the Mohonk Mountain House in the beautiful Hudson River Valley in upstate New York.
There will be a Short Course on October 6 2008.
The deadline for abstract submission is May 2 2008. Late papers with exceptional merit will be considered for the Late News Session if submitted on or before 25 August, 2008.
There is a Best Paper Award and also a Best Poster Award.
I remember that some papers on compact modeling won one of those awards, so it is a good topic for this conference.
The place of the Conference is very attractive. It is located atop of the Shawangunk Mountains. There is a very good offer of outdoor opportunities: hiking, lake swimming, boating, ...
The IEEE International SOI Conference is the main conference devoted to current trends in Silicon-on-Insulator technology. It provides an excellent forum for open discussion in all areas of SOI technologies and their applications.
The Areas of Focus of the IEEE International SOI Conference includes all topics related to SOI technologies, including "SOI device physics and modelingThere will be a Short Course on October 6 2008.
The deadline for abstract submission is May 2 2008. Late papers with exceptional merit will be considered for the Late News Session if submitted on or before 25 August, 2008.
There is a Best Paper Award and also a Best Poster Award.
I remember that some papers on compact modeling won one of those awards, so it is a good topic for this conference.
The place of the Conference is very attractive. It is located atop of the Shawangunk Mountains. There is a very good offer of outdoor opportunities: hiking, lake swimming, boating, ...
ESSDERC'08
ESSDERC 2008 will be held in Edinburgh, Scotland from 15-19 September 2008, together with ESSCIRC 2008 (European Solid-State Circuits Conference) . The venue will be the Edinburgh International Conference Centre (EICC).
ESSDERC (European Solid-State Device Research Conference) is the top European conference in semiconductor devices. Due to its prestige, many researchers from outside Europe use to submit contributions to ESSDERC too.
The main themes for original contributions to be submitted to ESSDERC 2008 are:
-Advanced Devices
-Process Integration
-Telecommunication & Power Devices
-Modeling and Simulation
-Charactrization and Reliability
-Memory, SoC & SiP
-Emerging Technologies, Sensors & Actuators
-Sensors and Imagers
-Integration of IC designs with other technologies and materials
-Yield and Reliability related technology developments
-Design for Manufacturabiliti
This year Compact Modeling is explicitly mentioned as one of the topics in the "Modeling and Simulation" theme.
The deadline for abstract submission is April 5 2008.
Besides, several related workshops will take place on September 19 2008 at the same location.
One of them will be the Autumn MOS-AK Meeting on Compact Modeling. Another workshop will be the so-called SINANO workshop, this time organized by the recently created SINANO Institute.
Ths social programme may be interesting this year. The Conference Dinner will be held at Murrayfield Stadium, the home of Scottish Rugby! And they say that the menu will be typically Scottish "preceded by a drinks reception". For sure, we expect a lot of high quality whisky during the Conference Dinner!
ESSDERC (European Solid-State Device Research Conference) is the top European conference in semiconductor devices. Due to its prestige, many researchers from outside Europe use to submit contributions to ESSDERC too.
The main themes for original contributions to be submitted to ESSDERC 2008 are:
-Advanced Devices
-Process Integration
-Telecommunication & Power Devices
-Modeling and Simulation
-Charactrization and Reliability
-Memory, SoC & SiP
-Emerging Technologies, Sensors & Actuators
-Sensors and Imagers
-Integration of IC designs with other technologies and materials
-Yield and Reliability related technology developments
-Design for Manufacturabiliti
This year Compact Modeling is explicitly mentioned as one of the topics in the "Modeling and Simulation" theme.
The deadline for abstract submission is April 5 2008.
Besides, several related workshops will take place on September 19 2008 at the same location.
One of them will be the Autumn MOS-AK Meeting on Compact Modeling. Another workshop will be the so-called SINANO workshop, this time organized by the recently created SINANO Institute.
Ths social programme may be interesting this year. The Conference Dinner will be held at Murrayfield Stadium, the home of Scottish Rugby! And they say that the menu will be typically Scottish "preceded by a drinks reception". For sure, we expect a lot of high quality whisky during the Conference Dinner!
Feb 12, 2008
DCIS'08
In 2008 DCIS (Conference on Design of Circuits and Integrated Systems) will take place in Grenoble, in France, on November 12-14 2008. It will be organized by the TIMA Laboratory.
DCIS was originally the top Spanish Conference on Circuit Design. However, more than 10 years ago it became an international conference. Although often held in Spain it has also been organized in other countries not far from Spain, such as Portugal or France.
The Call for Papers mentions all topics related to Integrated Circuit and Systems Design. As usual, modeling is included among the topics.
The submission deadline is April 4 2008.
Grenoble and its vicinity is a very nice place for sightseeing, offering many opportunities for outdoor: mountain trails to hike, historic buildings to see, old streets to walk along, and even skiing in the highest mountains in November.
DCIS was originally the top Spanish Conference on Circuit Design. However, more than 10 years ago it became an international conference. Although often held in Spain it has also been organized in other countries not far from Spain, such as Portugal or France.
The Call for Papers mentions all topics related to Integrated Circuit and Systems Design. As usual, modeling is included among the topics.
The submission deadline is April 4 2008.
Grenoble and its vicinity is a very nice place for sightseeing, offering many opportunities for outdoor: mountain trails to hike, historic buildings to see, old streets to walk along, and even skiing in the highest mountains in November.
New modeling papers in Solid-State Electronics
The February 2008 issue of Solid-State Electronics includes several interesting papers on compact modeling of different devices.
"A new analytical compact model for two-dimensional finger photodiodes", by T. Naeve et al
"An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET", by H. Kaur et al
"Extraction of series resistance using physical mobility and current models for MOSFETs", by H. Katto
"An explicit surface-potential-based model for undoped double-gate MOSFETs", by J. F. Gong et al
"An efficient channel segmentation approach for a large-signal NQS MOSFET model" by M. Bucher and A. Bazigos. This is a very interesting paper presenting an adequate technique to extend a compact Quasi-Static model to the RF operation.
I also recommend the following paper for reading (it is modeling of balistic devices although not compact modeling)
"Modeling the effects of the channel electron velocity on the channel surface potential of ballistic MOSFETs", by L. F. Mao
And there is a very interesting paper studying the capacitance characteristics of pentacene TFTs:
"Quasi-static capacitance–voltage characterizations of carrier accumulation and depletion phenomena in pentacene thin film transistors", by Y. M. Chen et al
The January issue of Solid State Electronics included a quite interesting paper by Huaxin Lu, Bo Yu and Yuan Taur, presenting a unified charge modelling formulation valid for both Double-Gate and Surrounding Gate MOSFETs:
"A unified charge model for symmetric double-gate and surrounding-gate MOSFETs", by Huaxin Lu, Bo Yu and Yuan Taur
A few compact modeling papers were also published in the December issue of Solid-State Electronics:
First of all, a compact model for power MOSFETs:
"An EKV-based high voltage MOSFET model with improved mobility and drift model", by Yogesh Singh Chauhan, Renaud Gillon, Benoit Bakeroot, Francois Krummenacher, Michel Declercq and Adrian Mihai Ionescu
And finally, a paper presenting an industrial view of compact modeling, indicating some special requirements that are important when developing physics-based compact models:
"An industrial view on compact modeling", by Reinout Woltjer, Luuk Tiemeijer and Dick Klaassen
"A new analytical compact model for two-dimensional finger photodiodes", by T. Naeve et al
"An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET", by H. Kaur et al
"Extraction of series resistance using physical mobility and current models for MOSFETs", by H. Katto
"An explicit surface-potential-based model for undoped double-gate MOSFETs", by J. F. Gong et al
"An efficient channel segmentation approach for a large-signal NQS MOSFET model" by M. Bucher and A. Bazigos. This is a very interesting paper presenting an adequate technique to extend a compact Quasi-Static model to the RF operation.
I also recommend the following paper for reading (it is modeling of balistic devices although not compact modeling)
"Modeling the effects of the channel electron velocity on the channel surface potential of ballistic MOSFETs", by L. F. Mao
And there is a very interesting paper studying the capacitance characteristics of pentacene TFTs:
"Quasi-static capacitance–voltage characterizations of carrier accumulation and depletion phenomena in pentacene thin film transistors", by Y. M. Chen et al
The January issue of Solid State Electronics included a quite interesting paper by Huaxin Lu, Bo Yu and Yuan Taur, presenting a unified charge modelling formulation valid for both Double-Gate and Surrounding Gate MOSFETs:
"A unified charge model for symmetric double-gate and surrounding-gate MOSFETs", by Huaxin Lu, Bo Yu and Yuan Taur
A few compact modeling papers were also published in the December issue of Solid-State Electronics:
First of all, a compact model for power MOSFETs:
"An EKV-based high voltage MOSFET model with improved mobility and drift model", by Yogesh Singh Chauhan, Renaud Gillon, Benoit Bakeroot, Francois Krummenacher, Michel Declercq and Adrian Mihai Ionescu
And finally, a paper presenting an industrial view of compact modeling, indicating some special requirements that are important when developing physics-based compact models:
"An industrial view on compact modeling", by Reinout Woltjer, Luuk Tiemeijer and Dick Klaassen
Feb 11, 2008
NANOSIL kick-off meeting
NANOSIL is the name of a new European Commission-funded Network of Excellence devoted to the research in nanodevices, mostly based on Silicon. NANOSIL is the continuation of a previous Network of Excellence called SINANO (2004-2007).
NANOSIL started on January 1 2008 and will have a duration of three years. The kick-off meeting took place in Grenoble (France) on January 29 2008.
NANOSIL aims to integrate the excellent European research laboratories and capabilities at the European level in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits. It will explore and assess all scientific and technological aspects of nanodevices (mostly based on Silicon) and operational regimes relevant to the 22nm technology node and beyond. Therefore, NANOSIL will provide a forward-look for the industry, enabling informed decisions to be taken on technology development to speed up technological innovation.
Compact modeling is one of the activities in the Flagship Projects. My group will be mostly involved in that task. We plan to develop compact models of the novel devices addressed by NANOSIL.
Besides, NANOSIL will organize workshops and a modeling summer school.
NANOSIL started on January 1 2008 and will have a duration of three years. The kick-off meeting took place in Grenoble (France) on January 29 2008.
NANOSIL aims to integrate the excellent European research laboratories and capabilities at the European level in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits. It will explore and assess all scientific and technological aspects of nanodevices (mostly based on Silicon) and operational regimes relevant to the 22nm technology node and beyond. Therefore, NANOSIL will provide a forward-look for the industry, enabling informed decisions to be taken on technology development to speed up technological innovation.
There are seven Flagship Projects in the areas of nanoscale CMOS (workpackage WP1) and post-CMOS (workpackage WP2), known as the “More Moore” and “Beyond-CMOS” domains. This work will be carried out through a network of joint processing, characterisation and modelling platforms. Alongside these technological Flagship Projects each workpackage also has a Visionary Project that will act as a forum to explore novel ideas bewteen academia and European industry.
The Flagship Projects will be "New Channel Materials" (including Strained SOI and GeOI devices), "Very Low Schottky Barrier MOSFETs", "Identification and appraisal of gate stack materials for the end of CMOS era", "Nanowires" (Silicon nanowires), "Carbon Electronics" (with emphasis on graphene devices), "Small slope nanoelectronic switch for low power integrated circuits”, and "Templated Self-Organization".
The Coordinator of NANOSIL will be Prof. Francis Balestra (INPG-MINATEC, Grenoble). A total 0f 28 European groups, including mine (URV, Spain), participate in NANOSIL.Compact modeling is one of the activities in the Flagship Projects. My group will be mostly involved in that task. We plan to develop compact models of the novel devices addressed by NANOSIL.
Besides, NANOSIL will organize workshops and a modeling summer school.
EUROSOI+
The European Commission approved in 2007 the funding of the continuation of EUROSOI, the European Thematic Network on SOI Technology, Devices and Circuits.
The new EUROSOI network will be called EUROSOI+ and will have aduration of three years, starting from January 1 2008.
The EUROSOI network organizes every year the EUROSOI workshop. This year it took place in Cork, Ireland, from January 23 to 25. The Chairman was Prof. Jean Pierre Colinge, from Tyndall National Institute (Cork).
The EUROSOI workshop is already consolidated as the main European event devoted to SOI technology, devices and circuits.
The kick-off meeting of the new EUROSOI+ network took place during the workshop. The coordinator of EUROSOI+ is Prof. Francisco Gamiz, from the University of Granada (SPAIN). He was also the coordinator of the previous EUROSOI network.
The members of EUROSOI+ are: University of Granada (Spain), INPG (France), UCL (Belgium), SOITEC (France), VTT (Finland), CISSOID (Belgium), IMEC (Belgium), Philips (The Netherlands), EPFL (Switzerland), ISP-Kiev (Ukraine), IUE (Austria), WUT (Poland), XFAB (Germany), Chalmers (Sweden), Uppsala University (Sweden), Queens University of Belfast (UK), University of Twente (The Netherlands), CNRS (France), IMMS (Germany), CSIC (Spain), University of Liverpool (UK), POLITO (Italy), Universitat Rovira i Virgili (Spain), Umiversitat Autonoma de Barcelona (Spain), Universidad de Salamanca (Spain), UNIUD (Italy), Ditocom (France), CEA-LETI (France), ISEP (France) and Tyndall National Institute (Ireland).
The main goals of EUROSOI+ will be to support and increase collaborations between European groups regarding research in SOI technology, and to elaborate a roadmap and a state of the art documents about SOI technology. The website of EUROSOI is regularly update to include all news related to SOI.
Compact modeling of SOI devices is one of the topics addressed by EUROSOI+. Actually, I will be mostly in charge of the writing of the parts related to compact modeling in the roadmap and a state of the art documents.
The EUROSOI workshop in Cork was interesting and of real high level. Every participant got a gift that was very useful in Ireland: an umbrella.
The new EUROSOI network will be called EUROSOI+ and will have aduration of three years, starting from January 1 2008.
The EUROSOI network organizes every year the EUROSOI workshop. This year it took place in Cork, Ireland, from January 23 to 25. The Chairman was Prof. Jean Pierre Colinge, from Tyndall National Institute (Cork).
The EUROSOI workshop is already consolidated as the main European event devoted to SOI technology, devices and circuits.
The kick-off meeting of the new EUROSOI+ network took place during the workshop. The coordinator of EUROSOI+ is Prof. Francisco Gamiz, from the University of Granada (SPAIN). He was also the coordinator of the previous EUROSOI network.
The members of EUROSOI+ are: University of Granada (Spain), INPG (France), UCL (Belgium), SOITEC (France), VTT (Finland), CISSOID (Belgium), IMEC (Belgium), Philips (The Netherlands), EPFL (Switzerland), ISP-Kiev (Ukraine), IUE (Austria), WUT (Poland), XFAB (Germany), Chalmers (Sweden), Uppsala University (Sweden), Queens University of Belfast (UK), University of Twente (The Netherlands), CNRS (France), IMMS (Germany), CSIC (Spain), University of Liverpool (UK), POLITO (Italy), Universitat Rovira i Virgili (Spain), Umiversitat Autonoma de Barcelona (Spain), Universidad de Salamanca (Spain), UNIUD (Italy), Ditocom (France), CEA-LETI (France), ISEP (France) and Tyndall National Institute (Ireland).
The main goals of EUROSOI+ will be to support and increase collaborations between European groups regarding research in SOI technology, and to elaborate a roadmap and a state of the art documents about SOI technology. The website of EUROSOI is regularly update to include all news related to SOI.
Compact modeling of SOI devices is one of the topics addressed by EUROSOI+. Actually, I will be mostly in charge of the writing of the parts related to compact modeling in the roadmap and a state of the art documents.
The EUROSOI workshop in Cork was interesting and of real high level. Every participant got a gift that was very useful in Ireland: an umbrella.
2008 Device Research Conference
The 2008 Device Research Conference (DRC 2008) will take place in the University of California, Santa Barbara, on June 23-25 2008.
DRC is one of the oldest conferences in the field of electron devices. Every year, DRC brings together top scientists, researchers and graduate students from both the industry and academia. Their latest research results are not only presented, but also frankly discussed. The fact that DRC is always held in one university encourages the exchange of creative ideas.
Student participation in DRC is always strong. Travel support for students is offered. Besides, there is a very prestigeous Best Student Paper Award.
The technical program will include oral and poster presentations as well as three rump sessions.
The deadline for abstract submission is March 7 2008.
Topics include all aspects related to electronic and optoelectronic devices, including "modeling and simulation of devices". The Call for Paper indicates with detail the types of devices addressed. Even biological devices are mentioned.
A number of prestigeous researchers will give invited talks.
Finally, there will be an excellent social programme, as can be expected when a conference takes place in a university.
DRC is one of the oldest conferences in the field of electron devices. Every year, DRC brings together top scientists, researchers and graduate students from both the industry and academia. Their latest research results are not only presented, but also frankly discussed. The fact that DRC is always held in one university encourages the exchange of creative ideas.
Student participation in DRC is always strong. Travel support for students is offered. Besides, there is a very prestigeous Best Student Paper Award.
The technical program will include oral and poster presentations as well as three rump sessions.
The deadline for abstract submission is March 7 2008.
Topics include all aspects related to electronic and optoelectronic devices, including "modeling and simulation of devices". The Call for Paper indicates with detail the types of devices addressed. Even biological devices are mentioned.
A number of prestigeous researchers will give invited talks.
Finally, there will be an excellent social programme, as can be expected when a conference takes place in a university.
Feb 4, 2008
MOS-AK meeting in Eindhoven 1st announcement
The aim of the MOS-AK Meetings series is to provide an open forum for the presentation and discussion of recent research and development results in technology, physics, modeling and applications of advanced compact models. We will be focusing but not limiting the discussion to following topics:
* Advances in RF CMOS device characterization and modeling
* Compact model Verilog-AMS/VHDL-AMS standardization and validation
* Statistical modeling for nano CMOS/SOI technologies
The technical program of MOS-AK Meeting consists of one day of presentations given by noted academic and industry experts, also a posters session is foreseen:
http://www.mos-ak.org/eindhoven
The workshop program is still open and you are welcome to submit paper/poster and/or suggest other related topic for presentation and discussion. Selected papers will be published in the IJNM - MOS-AK publication partner.
Important dates:
----------------
* 2nd annoncement - February 25
* Final workshop program - March 24
* COMON kick-off meeting - April 3 at MiPlaza, Eindhoven
* MOS-AK Meeting - April 4 at MiPlaza, Eindhoven
Local Meeting Organizers:
-------------------------
Mark de Haas, Co-ordinator of Electronic Measurement Laboratory (MiPlaza)
Nick Campbell, Senior Communications Manager
Further information including recommended hotels and driving directions will be posted at our web site, soon; please visit regularly: http://www.mos-ak.org
Jan 30, 2008
SINANO Institute
The SINANO (SIlicon NANOdevices) Institute, a new European association for research in Nanoelectronics, has been created. The SINANO Institute is composed of 16 top European institutions in the field of Nanoelectronics, and is intended to be one of the top European centres in Nanoelectronics, together with IMEC, LETI and Fraunhofer Institute. The Founding Members of the SINANO Institute participated in the former European Network of Excellence called SINANO (2004-07).
The kick-off meeting of the SINANO Institute took place on January 28 in Grenoble (France). The Internal Regulations were approved. Prof. Francis Balestra (INPG, France) was elected Director of the SINANO Institute. Prof. Olof Engström (Chalmers, Sweden) was elected Chairman of the General Assembly. The elected members of the Governing Board were: Emmanuel Dubois (IEMN, France), Heinrich Kurz (RWTH-Aachen, Germany), Enrico Sangiorgi (IUNET, Italy), Denis Flandre (UCL, Belgium) and Evan Parker (University of Warwick, UK).
The SINANO Institute will participate as a single entity in international projects. The Institute will develop scientific collaborations between the associated Members and national and international public and private entities that operate in the field of Nanoelectronics. The Institute will also develop collaborations with the industry, aimed at the exploitation of new ideas and concepts, their demonstration in prototype form and technological transfer.
The Founding Members of the SINANO Institute are:
Université Catholique de Louvain (UCL, Louvain-la-Neuve, Belgium),
AMO GmbH (Gesellschaft für Angewandte Mikro- und Optoelektronik mbH,
Aachen, Germany),
Forschungszentrum Jülich GmbH (Jülich, Germany),
RWTH Aachen University, Institut für Halbleitertechnik (IHT, Aachen, Germany),
The kick-off meeting of the SINANO Institute took place on January 28 in Grenoble (France). The Internal Regulations were approved. Prof. Francis Balestra (INPG, France) was elected Director of the SINANO Institute. Prof. Olof Engström (Chalmers, Sweden) was elected Chairman of the General Assembly. The elected members of the Governing Board were: Emmanuel Dubois (IEMN, France), Heinrich Kurz (RWTH-Aachen, Germany), Enrico Sangiorgi (IUNET, Italy), Denis Flandre (UCL, Belgium) and Evan Parker (University of Warwick, UK).
The SINANO Institute will participate as a single entity in international projects. The Institute will develop scientific collaborations between the associated Members and national and international public and private entities that operate in the field of Nanoelectronics. The Institute will also develop collaborations with the industry, aimed at the exploitation of new ideas and concepts, their demonstration in prototype form and technological transfer.
The Founding Members of the SINANO Institute are:
Université Catholique de Louvain (UCL, Louvain-la-Neuve, Belgium),
AMO GmbH (Gesellschaft für Angewandte Mikro- und Optoelektronik mbH,
Aachen, Germany),
Forschungszentrum Jülich GmbH (Jülich, Germany),
RWTH Aachen University, Institut für Halbleitertechnik (IHT, Aachen, Germany),
Univ Rovira i Virgili (URV, Tarragona, Spain),
Consorzio Nazionale Interuniversitario per la Nanoelectronica (IUNET, Bologna, Italy),
Institut Polytechnique de Grenoble (INPG, Grenoble, France),
Université des Sciences et Technologies de Lille (USTL-IEMN, Lille, France),
IMEL, NCSR “Demokritos” (Athens, Greece),
Chalmers Tekniska Högskola AB (Göteborg, Sweden),
Kungliga Tekniska Högskolan (KTH, Stockholm, Sweden),
Wikipedia
A new update on the wikipedia: the entry for the EKV model now has been translated from English to Español, Ελληνικά, Polski, Italiano and Català. And there are more to come... I repeat my last call for colaboration: if any of you is interested in translating this (or other) entry into your native language, let us know once it is done...
Defects in organic electronic devices
A new paper has been recently published in physica status solidi (a): Defects in organic electronic devices, by T. P. Nguyen. I copy the abstract, but have a look at the paper:
"The performance of organic electronic devices depends strongly on the quality of the semiconductor used, and the transport process, in particular is greatly affected by the defect states of the material. Knowledge of trapping parameters is therefore of prime importance for studying organic devices. While defects in conventional semiconductors are well known and can be more or less controlled during processing, the formation of defects in organic materials is still not well understood, and consequently, it is difficult to control the defect states in organic devices. For defects that are electrically active or traps, techniques such as thermally stimulated currents, impedance spectroscopy, or deep level transient spectroscopy have been successfully used for determining the corresponding parameters (density, energy level, capture cross section). In this work, we review some fundamental aspects of trap analysis in organic devices by highlighting their role in the charge transport process in these materials. We present updated data from trap studies in polyfluorene derivative based diodes and we address specific problems in analyzing traps in polymers and organic semiconductors. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)"
Jan 29, 2008
Some new papers
Some recently published papers (not all of them strictly related to Compact Models, but worth reading)
Gate modulation in carbon nanotube field effect transistors based NH3 gas sensors
Ning Peng, Qing Zhang, Yi Chau Lee, Ooi Kiang Tan and Nicola Marzari
Extraction of device parameters from dark current-voltage characteristics of PV devices
Erees Q. B. Macabebe, E. Ernest van Dyk
Understanding negative capacitance effect using an equivalent resistor-capacitor circuit
H. L. Kwok
Electron transport of nanotube-based gas sensors: An ab initio study
Arta Sadrzadeh, Amir A. Farajian, and Boris I. Yakobson
Study of the ability to field emission from diamond - like carbon layers and carbon nanotubes
Ryszard Gronau, Jan Szmidt, Piotr Firek, Elżbieta Czerwosz, Dagmara Jarzyńska and Elżbieta Staryga
Gate modulation in carbon nanotube field effect transistors based NH3 gas sensors
Ning Peng, Qing Zhang, Yi Chau Lee, Ooi Kiang Tan and Nicola Marzari
Extraction of device parameters from dark current-voltage characteristics of PV devices
Erees Q. B. Macabebe, E. Ernest van Dyk
Understanding negative capacitance effect using an equivalent resistor-capacitor circuit
H. L. Kwok
Electron transport of nanotube-based gas sensors: An ab initio study
Arta Sadrzadeh, Amir A. Farajian, and Boris I. Yakobson
Study of the ability to field emission from diamond - like carbon layers and carbon nanotubes
Ryszard Gronau, Jan Szmidt, Piotr Firek, Elżbieta Czerwosz, Dagmara Jarzyńska and Elżbieta Staryga
Jan 25, 2008
ICOE'08
The 2008 International Conference on Organic Electronics (ICOE 2008) will be held in Eindhoven (The Netherlands) on June 16-19 2008. The conference will take place in the Auditorium in the High Tech Campus in Eindhoven.
The ICOE conference was created by means of the European Integrated Project called PolyApply, one of the major projects about organic electronics. It has become one of the main conferences on organic electronics.
ICOE covers all aspects of organic electronics including Materials and Chemistry, OTFTs, OLED, PV devices, device modeling, organic circuits and circuit design, manufacture as well as their inclusion in systems. Therefore, it can be a good conference to present papers about compact models of organic devices, since many organic circuit designers may attend ICOE.
The deadline for a 1-or 2-page abstract submission is February 1 2008.
The Conference Chair is Professor Bill Eccleston, from the University of Liverpool.
Eidhoven is a very interesting city to visit, especially those dates in June 2008...You will see the impressive atmosphere in The Netherlands during the EURO Cup 2008 Football Championship. I recommend to watch in a pub the mantch Netherlands vs Romania on June 17...
The ICOE conference was created by means of the European Integrated Project called PolyApply, one of the major projects about organic electronics. It has become one of the main conferences on organic electronics.
ICOE covers all aspects of organic electronics including Materials and Chemistry, OTFTs, OLED, PV devices, device modeling, organic circuits and circuit design, manufacture as well as their inclusion in systems. Therefore, it can be a good conference to present papers about compact models of organic devices, since many organic circuit designers may attend ICOE.
The deadline for a 1-or 2-page abstract submission is February 1 2008.
The Conference Chair is Professor Bill Eccleston, from the University of Liverpool.
Eidhoven is a very interesting city to visit, especially those dates in June 2008...You will see the impressive atmosphere in The Netherlands during the EURO Cup 2008 Football Championship. I recommend to watch in a pub the mantch Netherlands vs Romania on June 17...
Jan 24, 2008
Extended deadline for ICCDCS'08
An extended deadline has been announced for ICCDCS, until february, 4. The Seventh International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2008, which will be held in Cancún, México, April 28-30. This conference will be preceded by an IEEE EDS Mini-Colloquium, on Sunday April 27. More information can be found on the conference's web pages or in the call for papers.
Wikipedia entry for EKV
As a result of an initiative promoted by Wladek Grabinski, we're happy to announce that the wikipedia entry for the EKV Model has been translated from English into Spanish and Greek. As Wladek says, it's time for other languages to come in. If any of you are interested, please contact us or let us know of your work!
Jan 21, 2008
ULIS'08
The 2008 Ultimate Integration on Silicon (ULIS) Conference will take place in Udine (Italy) on March 13-14.
ULIS has become a very interesting open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.
The deadline for paper submissions has been extended to January 23.
Besides, this year edition will include a tutorial session on 'Process and Device Issues from a Circuit Point of View'.
Udine
Besides, the Gala Dinner will take place in the historical Villa Gallici Deciani.
ULIS has become a very interesting open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale silicon and silicon compatible devices in the More Moore, More than Moore and Beyond CMOS domains.
The deadline for paper submissions has been extended to January 23.
Besides, this year edition will include a tutorial session on 'Process and Device Issues from a Circuit Point of View'.
Besides, the Gala Dinner will take place in the historical Villa Gallici Deciani.
Jan 10, 2008
Seventh International Caribbean Conference on Devices, Circuits and Systems
Wishing all of you a very happy and prosperous New Year, I would like to remind you about the Seventh International Caribbean Conference on Devices, Circuits and Systems, ICCDCS 2008, which will be held in Cancún, México, April 28-30. This conference will be preceded by an IEEE EDS Mini-Colloquium, on Sunday April 27. More information can be found on the conference's web pages or in the call for papers.
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