1Department of Electrical, Computer, and Systems Engineering, RPI Troy, NY 12180, USA
2Department of Electronic Systems, NUST, O.S. Bragstads plass 2a, 7034 Trondheim, N
4Electronics of the Future, Inc., Vienna, VA 22181, USA
Mike BrinsonLondon Metropolitan University (UK)
Mansun ChanHong Kong University of Science & Technology (HK)
Benjamin IniguezUniversitat Rovira i Virgili, Tarragona (SP)
Sébastien MartinieCEA-Leti, Grenobel (F)
Yogesh ChauhanIIT Kanpur (IN)
Holger VogtFraunhofer IMS, Duisburg (D)
Kejun XiaNXP (USA)
Ashkhen YesayanInstitute of Radiophysics and Electronics National Academy of Sciences (AM)
Virtual Educational Event at ESSDERC/ESSCIRC
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Chhandak Mukherjee1, Guilhem Larrieu2 and Cristell Maneuxsup1
Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors
EuroSOI-ULIS 2020, Sep 2020, Caen (F)
1IMS Laboratory, University of Bordeaux, France
2LAAS-CNRS, Université de Toulouse, France
HAL: hal.archives-ouvertes.fr/hal-02869216
Abstract: This paper presents a physics based, computationally efficient compact modeling approach for 3D vertical gate-all-around junctionless nanowire transistor (JLNT) arrays designed for future high performance computational logic circuit. The model features an explicit continuous analytical form adapted for a 14 nm channel JLNT technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary logic circuit simulations have been performed for benchmarking performances of transistor logic circuits, such as inverters and ring oscillators, designed using the developed model.
Fig: The vertical JLNT: (a) SEM image of nanowire arrays,
(b) single nanowire showing its (c) gate formation
Acknowledgement: This work is supported by ANR under Grant ANR-18- CE24-0005-01
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Systematic Design of Analog CMOS Circuits
Dr. Paul Jespers, UCLouvain, Louvain-la-Neuve, Belgium
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Low-power Circuits for IoT
Dr. Jorge Fernandes, INESC-ID, Lisbon, Portugal.
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