[paper] 1T-1C Dynamic Random Access Memory

1T-1C Dynamic Random Access Memory: 

Status, Challenges, and Prospects 

Alessio Spessot and Hyungrock Oh 

(Invited Paper)

IEEE TED, 67(4), 1382–1393

DOI:10.1109/ted.2020.2963911 

Abstract: This article reviews the status, the challenges, and the perspective of 1T-1C dynamic random access memory (DRAM) chip. The basic principles of the DRAM are presented, introducing the key functional aspects and the structure of modern devices. We present the most relevant historical trends for different modules of the memory chip, such as access device and storage element, reviewing some of the technological challenges faced by industry to guarantee the device shrinking imposed by the economic law. The most recent solutions introduced by the industry in modern DRAM devices for the critical elements are presented. Finally, a survey of the most critical bottleneck for future development is presented, reviewing some of the potential trends and perspectives of DRAM development.

Fig: Review of the historical evolution trend for the cell access device. Various cell access device options are shown. The 4F2 is enabled by the vertical channel. Corresponding technology nodes are included. 

Acknowledgment: The authors would like to thank the imec Core Partners Program for the support. They would also like to thank N. Horiguchi, A. Furnemont, M. H. Na, E. Dentoni Litta, R. Ritzenthaler, and M. Popovici from imec, P. Fazan and C. Mouli from Micron, and C. Kim, Y. Son, and Y. Ji from SK Hynix for the interesting discussions.