[Kick-off] Chipdesign Germany

Chipdesign Germany

Das Netzwerk für Chipdesign in Deutschland

https://www.chipdesign-germany.de/

OnLine Registrierung: https://eveeno.com/auftaktchipdesigngermany

Juni 6. Donnerstag

13:00 Ankunft & Registrierung
14:00 Eröffnung
14:00 Begrüßung

Holger Blume; Leibniz Universität Hannover & edacentrum e.V.

14:15 Grußworte

Apollonia Pane Bundesministerium für Bildung und Forschung 

14:30 Vorstellung Chipdesign Germany

Holger Blume; Leibniz Universität Hannover & edacentrum e.V.
Norbert Wehn; Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau

14:45 Keynote-Session I

14:45 Open-Source EDA and Innovation Leadership
Andrew B. Kahng; University of California San Diego, US

15:45 Kaffeepause
16:30 Keynote-Session II

16:30 Open Source Chip Design: Europas Weg zur Wettbewerbsfähigkeit in einer geteilten Tech-Welt?

Jan-Peter Kleinhans; Stiftung Neue Verantwortung

17:30 Mikroelektronik in digitalen Hörhilfen: Chips, die hören helfen

Joachim Thiemann; Advanced Bionic

18:30 Networking-Veranstaltung mit Poster- & Demo-Session

Juni 7. Freitag

08:30 Eröffnung
08:30 Begrüßung

Holger Blume; Leibniz Universität Hannover & edacentrum e.V

08:45 Keynote-Session III
08:45 Neue Fertigungstechnik für die Chipverarbeitung

Lutz Rissing; Dr. Johannes Heidenhain GmbH

09:45 Kaffeepause
10:30 DE:Sign Präsentationen

BMBF-Förderlinie "Design-Instrumente für souveräne Chipentwicklung mit Open-Source (DE:Sign)"

10:30 DI-OCRCpro

Daniel Krupka; Gesellschaft für Informatik e.V.

10:45 DI-DEMICO

Frank Ellinger; Technische Universität Dresden

11:00 DI-DERAMSys

Matthias Jung; Julius-Maximilian-Universität Würzburg

11:15 DI-OWAS

Dirk Koch; Ruprecht-Karls-Universität Heidelberg

11:30 DI-PASSIONATE

Robert Weigel; Friedrich-Alexander Universität Erlangen-Nürnberg

11:45 Interaktive Poster-Session
13:30 Verabschiedung

Adresse: Königlicher Pferdestall - Leibniz Universität Hannover; Appelstr. 7, 30167 Hannover
OnLine Registrierung: https://eveeno.com/auftaktchipdesigngermany

Workshop on Advanced Integrated Circuit Design

U.S.-Japan Collaborative Workshop on Advanced Integrated Circuit Design

(Phase 2)

Fukuoka System LSI Development Center 2F

May 14 - May 15, 2024

https://www.kerc.or.jp/seminar/2024/04/5145152.html

In recent years, R&D and investment in semiconductors have become more active in countries around the world, and at the same time, the need for human resource development has been pointed out. In Japan in particular, the construction and attraction of factories for semiconductor "manufacturing" is accelerating, and various activities are being developed, but in the future, it is necessary to accelerate discussions on semiconductor "design". Against this backdrop, with the support of the U.S. Consulate in Fukuoka, we decided to hold a workshop in collaboration with the U.S. In December 2023, we held the U.S.-Japan Collaborative Workshop on Circuit Design (Phase 1), a state-of-the-art integrated circuit design, with the aim of learning about the latest situation in both countries through lectures on cutting-edge design technology and human resource development in Japan and the United States, as well as discussing the future direction and possibilities for international collaboration. We cover a wide range of topics, including open IC design, advanced analog and digital circuit design, generative AI processing (LLM) acceleration, optical circuit design, cryogenic classical and quantum computing, and new device technologies. Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars), free of charge, with simultaneous English-Japanese interpretation. Therefore, it is a form that is easy to participate in. This is a good opportunity to learn about global trends, so not only those who specialize in semiconductors, but also those who are even a little interested in semiconductors, please join us. Students are also welcome to participate! In addition, we plan to have a simple hands-on session in the tutorial session, so if you are interested, please bring / prepare a laptop.

Outline of the event

Date & Time

DAY-1: May 14, 2024 10:00 a.m. ~ 4:00p.m.
DAY-2: May 15, 2024 10:00 a.m. ~ 4:05 p.m.

Hybrid format (lectures can be held at Fukuoka venues and ZOOM Webinars)
Online (Zoom Webinars)

Fukuoka Venue: Fukuoka System LSI Development Center 2F
(〒814-0001 3-8-33 Momochihama, Sawara-ku, Fukuoka City)
There is no parking lot at the venue, so if you come by car, please use the
nearby paid parking lot.

Participation Fee:  free

Application
[Application deadline: May 13]
Please apply from the link below (you can also apply for either Day-1 or Day-2 only). Simultaneous interpretation in English and → is available at the Fukuoka venue and ZOOM Webinars. The first 70 people to participate at the Fukuoka venue and the first 400 people to participate in the ZOOM Webinar will be closed to the first 400 people. If you wish to cancel after applying for the Fukuoka venue, please contact us as soon as possible. In addition, we are planning a simple hands-on, so please bring your laptop (you can participate without a laptop).

Application Form

Program Details  (subject to update) https://www.kerc.or.jp/seminar/2024/04/5145152.html

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Day-1: May 14, 10:00-16:00 (JST)

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10:00 - 10:05 Opening Remark and Overview of the Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

[Morning Session: Invited Talks]
10:05 - 10:10 Welcome Remarks from the U.S. Consulate in Fukuoka
10:10 - 10:55 LLMs on ASICs, Greg Kielian/Kauna Lei, Google Research
11:00 - 11:45 Teaching Mixed-Signal Design Using Open-Source Tools, Boris Murmann, University of Hawaii
11:45 - 13:00 Lunch Break

[Afternoon Session: Tutorials]
13:00 - 14:00 Photonic and Analog circuits with GDSFactory, Joaquin Matres/Troy Tamas, Google X/DoPlayDo, Inc.
14:00 - 14:15 Break
14:15 - 15:45 ReaLLMASIC: Build your own Lightweight LLM, Gregory Kielian/Kauna Lei/Shiwei Liu/Mehdi Saligane, Google Research/University of Michigan
15:45 - 16:00 Conclusion, Mehdi Saligane, University of Michigan

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Day-2: May 15th, 10:00-16:05 (JST) 

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10:00 - 10:05 Opening Remark and Overview of Day-2 Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University
[Morning Session: Invited Talks]
10:05 - 10:50 Superconductor Computer Architecture: from Classical to Quantum, Ilkwon Byun, Kyushu University
10:50 - 11:35 Overview of new devices in the era of Beyond CMOS, Sadayuki Yoshitomi, Megachips
11:35 - 13:00 Lunch Break
[Afternoon Session: Tutorials]
13:00 - 13:55 (Tentative: GLayout), Anhang Li/Boris Murmann/Mehdi Saligane, University of Michigan/University of Hawaii
13:55 - 14:50 (Tentative: XLS: High-Level Synthesis), Johan Euphrosine, Google
14:50 - 15:05 Break
15:05 - 16:00 Pitfalls of Open-Source Chip Design Verification, Mitch Bailey, Efabless/ShuhariSystem
16:00 - 16:05 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

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Organizer

University of Michigan
Kyushu University System LSI Research Center Kyushu University
Quantum Computing Systems Research Center Kyushu University
Value Creation Semiconductor Human Resource Development Center

Co-organizers
Fukuoka Prefectural Foundation for the Promotion of Industry, Science and Technology Kyushu Economic Research Association

Sponsor
U.S. Consulate in Fukuoka

Inquiries
ic-design-ws 'at' slrc.kyushu-u.ac.jp (replace 'at' with @)
Okano, Business Development Department, TEL: 092-721-4907

In Memoriam: Willy Sansen (1943-2024)

In Memoriam: Willy Sansen (1943-2024)

// by caeleste.be/

We are deeply saddened to announce the passing of Willy Sansen, Emeritus Professor of Engineering Science at KU Leuven and esteemed member of the Board of Directors at Caeleste.

With heavy hearts, we say farewell to a true visionary and leader in the field of engineering. Throughout his distinguished career, Willy's contributions to both academia and industry were immeasurable.

As a professor, he inspired generations of students with his passion for research and teaching. As a member of our board, his guidance and expertise were instrumental in shaping the direction of Caeleste.

Willy's legacy will forever endure through the lives he touched and the knowledge he shared. Our thoughts are with his family and loved ones during this difficult time.

Rest in peace, Willy Sansen.
Your impact will continue to inspire us all.

[paper] Compact Modeling of Hysteresis in OTFTs

Compact modeling of hysteresis in organic thin-film transistors

A. Romero^a, J.A. Jiménez-Tejada^a, R. Picos^b, D. Lara^a, J.B. Roldán^a, M.J. Deen^c

Organic Electronics 129 (2024) 107048

DOI : 10.1016/j.orgel.2024.107048

a Departamento de Electrónica y Tecnología de Computadores, CITIC-UGR, Uni Granada, Spain
b Department of Industrial Engineering and Construction, Universitat de les Illes Balears, Spain
c Department of Electrical and Computer Engineering, McMaster University, Canada

Abstract: In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization and modeling of memory transistors. The model is expressed as a first-order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time-dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics

FIG: a.) Modeling the contact regions and intrinsic channel of an OTFT structure (a bottom contact configuration); b.)  Comparison of experimental transfer characteristics

Acknowledgements : The authors acknowledge support from the project PID2022 139586NB-44 funded by MCIN/AEI/10.13039/501100011033 and FEDER, EU. Funding for open access charge: Universidad de Granada / CBUA.

Appendix: Supplementary material related to this article can be found online.

[PhD] Transient Simulation of Frequency Domain Devices in Gnucap

Adding transient simulation of frequency domain devices to the Gnucap circuit simulator

Phd Thesis by Seán Higginbotham

Supervisor: Assistant Prof. Justin King

April 2024

Trinity College Dublin, The University of Dublin

College Green, Dublin 2, Ireland

Abstract: Radio frequency design constitutes a dominant element in the development of key communications technologies. Having accurate, robust, and widely accessible simulation methods is critical to ensuring continued advancements in this field, and guaranteeing the associated infrastructural and societal shifts that such technologies enable.

High frequency circuits invariably contain multiple non-linear components, which are naturally dealt with via time marching simulation of their time-domain analytic equations. However, including this alongside linear, generally dispersive, devices and effects, which are typically only characterised through a set of frequency-domain data describing the scattering response of an associated port-network, has traditionally been a problem for designers. Frequency-domain methods such as the harmonic balance technique and its successors have dominated radio frequency design for decades. However, such methods exhibit disadvantages in the context of modern circuits which are increasingly non-linear, and which operate with increasingly complicated modulated signals.

Various alternatives have been proposed, though as of yet no universally accepted method has emerged. Though harmonic balance will likely not be replaced, this project seeks to implement one such pure transient technique as an alternative. The proposed technique is based on using the vector-fitting algorithm to produce a model of the frequency response of the linear portnetwork, and then using a recursive convolution formulation to allow the time-domain response to be efficiently obtained from the port’s impulse response. An equivalent circuit companion model is developed from the resulting time-domain power-wave relation. This companion model allows the linear device to be directly included in a transient simulation alongside the analytic non-linear components, by way of providing a manner of computing the voltage and current on the network’s ports.

We implement the technique for one-port networks in a circuit driven by baseband signals. It is added to the free, open-source Gnucap circuit simulator as a ‘device plugin’. This report details how the implementation was done and provides results illustrating that it works as intended; the plugin can be installed by a user, who simply provides it with a file of frequency-domain data representing the port-network, and the plugin works naturally with the Gnucap transient solver to allow obtaining a transient solution of the overall circuit. A pure transient technique such as this does not require limiting assumptions or approximations on any components in the circuit and they are therefore preferable in certain contexts to frequency-domain methods like harmonic balance.

The project offers a significant contribution towards increasing the accessibility of radiofrequency electronics design and teaching.

 FIG: Summary of the traditional approach to simulating RF/MW circuits via HB, and the proposed pure transient approach implemented in this PhD Thesis

Acknowledgements: Seán Higginbotham would like to thank my M.A.I supervisor Dr. Justin King, whose previous work was the basis for this project. He provided invaluable insights and guidance which made the project both possible and an enjoyable experience, instilling curiosity at each discussion. Relevant academic references are included in the bibliography section. Acknowledgements of the dependancies used in the project code follow.

Gnucap is the creation of Albert Davis and is developed by him and others. It is provided under the GNU GPLv3, which is also the license that this project code is provided under on the associated GitHub repository.

See https://www.gnu.org/licenses/gpl-3.0.html. For the GNU GPLv3 license. Additionally, see the Gnucap repository here https://savannah.gnu.org/projects/ gnucap/.

LAPACK is a co-creation of The University of Tennessee and The University of Tennessee Research Foundation, The University of California Berkeley, and The University of Colorado Denver. See the user guide here https://netlib.org/lapack/.

The LAPACKE C bindings are the creation of Intel Corp.

The relevant licensing files are found within the source code and on the respective website.

Should the reader of this report have any questions or suggestions, please feel free to reach out at higginbs@tcd.ie, or via other channels such as the project GitHub located at https: //github.com/SHigginbotham/transient-sparam-gnucap. The project supervisor may also be of interest, available at justin.king@tcd.ie.