FOSS Circuit Simulators

AN OPEN-SOURCE, FREE CIRCUIT SIMULATOR

by: Bryan Cockfield on July 30, 2023

The original circuit simulation software, called the Simulation Program with Integrated Circuit Emphasis, or SPICE as it is more commonly known, was originally developed at the University of Califorina Berkeley in the 1970s with an open-source license. That’s the reason for the vast versions of SPICE available now decades after the original was released, not all of which are as open or free as we might like [1].

Fig: The Quite Universal Circuit Simulator includes a GUI based on the Qt toolkit and handles ad and ac analysis, S-parameters, harmonic balance analysis, noise analysis, and so forth. 

We’ve [2] listed all the simulators we found - the good, the bad, and the ugly - that actually did perform circuit simulation in some fashion. They are provided alphabetically, along with the most notable benefits and drawbacks we uncovered.

REF:
[1] An Open-Source, Free Circuit Simulator by Bryan Cockfield on July 30, 2023
[2] Best free analog circuit simulators by Lee Teschler on January 26, 2022

[book] Organic and Inorganic Light Emitting Diodes

Organic and Inorganic Light Emitting Diodes
Reliability Issues and Performance Enhancement

Edited By T.D. Subash, J. Ajayan, W. Grabinski

ISBN 9781032375175 1st Edition (C) 2023
198 Pages 106 B/W Illustrations
Published June 19, 2023 by CRC Press

Description

This book covers a comprehensive range of topics on the physical mechanisms of LEDs (light emitting diodes), scattering effects, challenges in fabrication and efficient enhancement techniques in organic and inorganic LEDs. It deals with various reliability issues in organic/inorganic LEDs like trapping and scattering effects, packaging failures, efficiency droops, irradiation effects, thermal degradation mechanisms, and thermal degradation processes.

Chapter 1: Fundamental Physics of Light Emitting Diodes: Organic

and Inorganic Technology; Deboraj Muchahary, Sagar Bhattarai, Arvind Sharma and Ajay Kumar Mahato

Chapter 2: Physical Mechanisms That Limit the Reliability of LEDs; Tulasi Radhika Patnala, N. Hemalatha, Sankararao Majji and M. Sundar Rajan

Chapter 3: Scattering Effects on the Optical Performance of LEDs; Vinodhini Subramaniyam, B. A. Saravanan and Moorthi Pichumani

Chapter 4: Challenges in Fabrication and Packaging of LEDs; Nesa Majidzadeh and Hossein Movla

Chapter 5: Opportunities and Challenges in Flexible and Organic LED; Shalu C.

Chapter 6: Light Extraction Efficiency Improvement Techniques in Light-Emitting Diodes; M. Manikandan, G. Dhivyasri, D. Nirmal, Joseph Anthony Prathap and Binola K. Jebalin I. V.

Chapter 7: Efficiency Enhancement Techniques in Flexible and Organic Light-Emitting Diodes; J. Ajayan and T. D. Subash

Chapter 8: Performance Enhancement of Light Emitting Radiating Dipoles (LERDs) Using Surface Plasmon-Coupled and Photonic Crystal-Coupled Emission Platforms; Seemesh Bhaskar and Sai Sathish Ramamurthy

[paper] THz FET Modeling

Adam Gleichman¹, Kindred Griffis¹, and Sergey V. Baryshev^1,2

Useful Circuit Analogies to Model THz Field Effect Transistors

arXiv:2307.07488v1 [physics.app-ph] 14 Jul 2023

1) Department of Electrical and Computer Engineering, Michigan State University, USA
2) Department of Chemical Engineering and Materials Science, Michigan State University, USA

Anstract: The electron fluid model in plasmonic field effect transistor (FET) operation is related to the behavior of a radio-frequency (RF) cavity. This new understanding led to finding the relationships between physical device parameters and equivalent circuit components in traditional parallel resistor, inductor, and capacitor (RLC) and transmission models for cavity structures. Verification of these models is performed using PSpice to simulate the frequency dependent.

FIG: RLC Lumped THz FET Model

[paper] artificial synapse

Md. Hasan Raza Ansari, Udaya Mohanan Kannan, and Nazek El-Atab

Silicon Nanowire Charge Trapping Memory for Energy-Efficient Neuromorphic Computing

IEEE Transactions on Nanotechnology (2023)

DOI 10.1109/TNANO.2023.3296673

SAMA Labs, CEMSE Division, KAUST, Thuwal 23955-6900, Saudi Arabia

Department of Electronic Engineering, Gachon University, Seongnam 13120, Korea

Abstract: This work highlights the utilization of the floating body effect and charge-trapping/de-trapping phenomenon of a Silicon-nanowire (Si-nanowire) charge-trapping memory for an artificial synapse of neuromorphic computing application. Charge trapping/de-trapping in the nitride layer characterizes the long-term potentiation (LTP)/depression (LTD). The accumulation of holes in the potential well achieves short-term potentiation (STP) and controls the transition from STP to LTP. Also, the transition from STP to LTP is analyzed through gate length scaling and high-κ material (Al2O3) for blocking oxide. Furthermore, the conductance values of the device are utilized for system-level simulation. System-level hardware parameters of a convolutional neural network (CNN) for inference applications are evaluated and compared to a static random-access memory (SRAM) device and charge-trapping memory. The results confirm that the Si-nanowire transistor with better gate controllability has a high retention time for LTP states, consumes low power, and archives better accuracy (91.27%). These results make the device suitable for low-power neuromorphic applications.

FIG: Schematic representation of biological and Si-nanowire charge trapping memory as an artificial synapse

[paper] TMD FETs

Ahmed Mounir^a, Benjamin Iñiguez^a, François Lime^a, Alexander Kloes^b

Theresia Knobloch^c, Tibor Grasser^c

Compact I-V model for back-gated and double-gated TMD FETs

Solid-State Electronics (2023): 108702

DOI: 10.1016/j.sse.2023.108702

a Rovira I Virgili University, Tarragona, Spain
b University of Applied Sciences, Giessen, Germany
c TU Wien, Vienna, Austria

Abstract: A physics-based analytical DC compact model for double and single gate TMD FETs is presented. The model is developed by calculating the charge density inside the 2D layer which is expressed in terms of the Lambert W function that recently has become the standard in SPICE simulators. The current is then calculated in terms of the charge densities at the drain and source ends of the channel. We validate our model against measurement data for different device structures. A superlinear current increase above certain gate voltage has been observed in some MoS2 FET devices, where we present a new mobility model to account for the observed phenomena. Despite the simplicity of the model, it shows very good agreement with the experimental data.

Fig : 2D schematic structure for 2D TMD FETs: (a) a double gated monolayer MoS2 FET. 

(b) a double gated monolayer WSe2 FET. (c)  single back-gated multilayer MoS2 FET. 

(d) single back-gated monolayer FET.