[paper] Modeling of SIC VDMOS FET

Anirban Kar∗, Ahtisham Pampori∗, Noriyoshi Hashimoto† and Yogesh Singh Chauhan∗

A Charge-Based Silicon Carbide MOSFET Compact Model for Power Electronics Applications

2021 IEEE 8th Uttar Pradesh Section UPCON)

DOI: 10.1109/UPCON52273.2021.9667643

∗Department of Electrical Engineering, IIT Kanpur (IN)
†Keysight Technologies (J)

Abstract: This paper presents a charge-based compact model for Silicon Carbide (SiC) power MOSFETs, which captures the static characteristics of the device over a wide range of voltages and currents. The drift region resistance and charges in the channel have been formulated to calculate the drain current in a self-consistent manner. The proposed model has been validated against the measured transfer and output characteristics of a commercial 1.2kV power MOSFET (Infineon IMW120R045M1) with a maximum current rating of 52A.

Fig: a) Transfer characteristics of SiC MOSFET with Vd=1 to 20V

b) Transconductance of SiC MOSFET with Vd=1 to 20V 

Acknowledgement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA02/2017-18 and in part by the Department of Science and Technology through the FIST Scheme under Grant SR/FST/ETII-072/2016 and Keysight Technologies, USA. The measurement of the device was carried out at Keysight Technologies, Japan.

IEEE SSCS PICO Contestants Cross the Finish Line

by Boris Murmann

DOI:10.1109/MSSC.2021.3135176

Date of current version: 24 January 2022

Last summer 2021, the IEEE Solid-State Circuits Society (SSCS) launched its first open source chip design contest under the umbrella of its Platform for Integrated Circuit Design Outreach program (PICO). Beginning with 61 submissions, a volunteer jury selected 18 teams from nine countries to embark on a journey toward tapeout. Anyone interested in supporting future activities is encouraged to sign up at the Society’s volunteer web portal. Stay tuned for the 2022 edition of the SSCS PICO contest!

FIG: Layout views of the chips submitted for tape out

      TABLE: A Summary Oof Designs Submitted for TapeOut

	Function	Team	Chip URL
1	5G bidirectional amplifier	Pakistan 3 (National University of Computer and Emerging Sciences)	https://efabless.com/projects/560
2	Wireless power transfer unit	Pakistan 2 (National University of Computer and Emerging Sciences)
3	Variable precision fused multiply–add unit	Pakistan 1 (National University of Computer and Emerging Sciences)
4	Oscillator-based LVDT readout	India 2 (Anna University)	https://efabless.com/projects/474
5	Temperature sensor	India 1 (Anna University)
6	GPS baseband engine	India 3 (Anna University)
7	Ultralow-power analog front end for bio signals	Brazil 2 (Universidade Federal de Santa Catarina)	https://efabless.com/projects/476
8	TIA for quantum photonics interface	USA 4 (University of Virginia)	https://efabless.com/projects/470
9	Bandgap reference	Egypt (Cairo University)	https://efabless.com/projects/473
10	Neural network for sleep apnea detection	USA 2 (University of Missouri)
11	Sonar processing unit	Chile (University of the Bío-Bío)	https://efabless.com/projects/54

[Google Research] Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning #semi https://t.co/BD4iXWv5aS

[Google Research] Releases Circuit Training, an Open-Source Framework for Automated Chip Floorplanning #semi https://t.co/BD4iXWv5aS

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[paper] Implementation of Low Power Inverter using JL DG TFET

Sabitabrata Bhattacharya and Suman Lata Tripathi

Implementation of Low Power Inverter 

using Si1‑xGex Pocket N & P‑Channel Junction‑Less Double Gate TFET

Silicon, Springer Nature B.V. 2021

Received: 19 October 2021 / Accepted: 16 December 2021

DOI: 10.1007/s12633-021-01628-w

  

* School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India

Abstract: In this paper tunnel field effect transistor is reintroduced as an efficient low power replacement of MOSFET. The main draw- backs of TFET devices, like low ON-state current and low ION/IOFF ratio, are removed by structural and material modifica- tions. The proposed device is named junction-less double gate TFET or JL DGTFET. The junction-less attribute is used to reduce fabrication complexity, double gate is used to have better control over channel conduction and enhance drive current, high k gate dielectric and high work function gate metal is used to increase ON current. Low band gap Si1-xGex pocket is used near source end of the device to further improve performance. Four-fold optimization of the device is done along with temperature analysis to propose the best possible structure and dimensions. The proposed junction-less DGTFET was found to show huge performance improvement in ION/IOFF (of the order of 1011) and short channel parameters (SS = 63.5 mV/dec- ade, DIBL = 22.2 mV/V) over existing TFET devices. Both N & P-channel of the device is implemented with the optimised values on 18 nm technology node. Finally, an inverter circuit using both the N & P-channel devices is implemented following the CMOS compatible structure, and it is found to give very good results at low power.

Fig: Design of inverter circuit using n-JL DGTFET and p- JL DGTFET

Acknowledgements: The authors acknowledge for the support and lab facility provided by department of VLSI design, School of Electronics and Electrical Engineering, Lovely Professional University, Punjab India.

American chip-making giant Intel is a shadow of its former self

[Naveed Sherwani] American chip-making giant Intel is a shadow of its former self Details: https://t.co/79n7d6rQJI #semi https://t.co/mkWoP5ms5t

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