Virtual Si Museum /2101/ Electron Devices Time Line

my own view on the electron devices time line. The electron devices scaling: from a single vacuum tube, a BJT, TTL digital ICs to 68719476736 devices in a NAND flash memory card. If you have something else to add, just let me know:

REF:

1. Vacuum Tube GE 9-22 188-5
2. 2N2905A BJT - PNP, -60 V, -600 mA, 600 mW, TO-39
3. TTL 74F00 IC - 5V, quad 2-input NAND gate; series F (=fast) introduced in 1978
4. 64Gb NAND flash memory card

[Opinion] Money's not the problem for Europe's #semi rebuild https://t.co/5zyzOORFMi https://t.co/UYXWPxzXac

[Opinion] Money's not the problem for Europe's #semi rebuild https://t.co/5zyzOORFMi pic.twitter.com/UYXWPxzXac

— Wladek Grabinski (@wladek60) January 6, 2021

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January 06, 2021 at 02:13PM
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[paper] Perspective of Ultra-Scaled CMOS

Ab initio perspective of ultra-scaled CMOS

from 2D-material fundamentals to dynamically doped transistors

Aryan Afzalian 

Open Access; npj 2D Mater Appl 5, 5 (2021) 

DOI: 10.1038/s41699-020-00181-1 

Abstract: Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Fig: Switching energy vs delay (EDP) of high-performance MOSFET and D2-FET inverters. EDP of 1ML-HfS2 high-performance inverter cells, at various VDD (0.4 V to 0.7 V), made of L = 5 nm and L = 3 nm stacked DG MOSFETs (5 ribbons/device) and L = 0 nm and L = nm stacked SG-D2-FETs (nine ribbons/device). The EDP performance of Si HP inverter cells made of L = 12 nm stacked Si-GAA MOSFETs (tS = 5 nm, 8 wires/device) and L = 5 nm stacked Si SG-D2-FETs (tS = 3 nm, 7 ribbons/device) are also shown for comparison. The inverters are loaded with a 50 contacted-gate-pitch-long metal line (https://irds.ieee.org/editions/2018). The extrinsic capacitances of the cell layout are also included in the load capacitance. IOFF = 10 nA/μm. ΔL = 4 nm for the D2-FETs.

Acknowledgements: Part of the computing resources and services used in this work were provided by the VSC (Flemish Supercomputer Center), funded by the Research Foundation–Flanders (FWO) and the Flemish Government. The author acknowledges the support of Dr. G. Gaddemane for the DFTP e-ph coupling calculations.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

[paper] NESS Open-Source TCAD Environment

Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Ali Rezaei, Daniel Nagy,

Vihar P. Georgiev, and Asen Asenov

Nano-Electronic Simulation Software (NESS): 

A Novel Open-Source TCAD Simulation Environment

Journal of Microelectronic Manufacturing

Vol 3 (4) : 20030407 2020

DOI:  10.33079/jomm.20030407

Abstract: This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software (NESS) which is currently under development at the Device Modeling Group of the University of Glasgow. NESS is designed with the main aim to provide an open, flexible, and easy to use simulation environment where users are able not only to perform numerical simulations but also to develop and implement new simulation methods and models. Currently, NESS is organized into two main components: the structure generator and a collection of different numerical solvers; which are linked to supporting components such as an effective mass extractor and materials database. This paper gives a brief overview of each of the components by describing their main capabilities, structure, and theory behind each one of them. Moreover, to illustrate the capabilities of each component, here we have given examples considering various device structures, architectures, materials, etc. at multiple simulation conditions. We expect that NESS will prove to be a great tool for both conventional as well as exploratory device research programs and projects.

Fig: Randomly generated atomistic device considering random discrete dopants (RDD) and metal gate granularity (MGG) in the NESS simulation domain

Acknowledgments: This project was initiated by the European Union Horizon 2020 research and innovation programme under grant agreement No. 688101 SUPERAID7 and has received further funding from EPSRC UKRI Innovation Fellowship scheme under grant agreement No. EP/S001131/1 (QSEE), No. EP/P009972/1 (QUANTDEVMOD) and No. EP/S000259/1 (Variability PDK for design based research on FPGA/neuro computing); and from H2020-FETOPEN-2019 scheme under grant agreement No.862539-Electromed-FET OPEN. The coauthors would like to thank Dr. Carrillo-Nuñez, Dr. Lee, Dr. Berrada, Dr. Badami, and Dr. Duan for their former contribution to NESS; as well as Dr. Donetti for the possibility of using the 1DMC tool. 

[paper] Analysis of 2D Transistors

Guoli Li, Zizheng Fan, Nicolas André, Member, IEEE, Yongye Xu, Ying Xia, Benjamín Iñíguez, Fellow, IEEE, Lei Liao, Senior Member, IEEE, and Denis Flandre, Senior Member, IEEE

Non-Linear Output-Conductance Function for Robust Analysis of Two-Dimensional Transistors

IEEE Electron Device Letters, 42(1), pp.94-97

DOI: 10.1109/LED.2020.3042212

Abstract: In this work, we explore the outputconductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the currentvoltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

G-Function Model (for Linear and Non-Linear Cases), the Rch and Rc can be calculated for both the Ohmic and Schottky contacts in the 2D transistors: 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2018YFA0703700; in part by the National Natural Science Foundation of China under Grant 61925403, Grant 61851403, and Grant 62004065; in part by the Hunan Natural Science Foundation under Grant 2020JJ5087; and in part by the Technology Program (Major Project) of Changsha under Grant kq1902042.