Flavien Cozette1, Bilal Hassan1, Christophe Rodriguez1, Eric Frayssinet2, Rémi Comyn2, François Lecourt3, Nicolas Defrance4, Nathalie Labat5, François Boone1, Ali Soltani1, Abdelatif Jaouad1, Yvon Cordier2 and Hassan Maher1
New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor
2021 Semicond. Sci. Technol. 36 034002
DOI: 10.1088/1361-6641/abd489
1LN2, CNRS-UMI-3463, 3IT, Université de Sherbrooke, Canada
2Université Côte d'Azur, CNRS, CRHEA, Valbonne, France
3OMMIC, 94450 Limeil-Brévannes, France
4IEMN, CNRS-UMR-8520, University of Lille, France
5IMS, CNRS-UMR-5218, University of Bordeaux, France
Abstract: This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (Vth) of +0.4 V and +0.9 V respectively with ΔVth about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an ION/IOFF about 108 and a breakdown voltage of VBR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.
Fig: SEM image of an E-mode device.
Acknowledgments: This work was supported by Fonds de Recherches du Québec—Nature, Technologies (FRQNT), the Natural Sciences and Engineering Research Council of Canada (NSERC), French technology facility network RENATECH and the French National Research Agency (ANR) through the projects ED-GaN (ANR-16-CE24-0026-02) and the 'Investissements d'Avenir' program GaNeX (ANR-11-LABX-0014).
