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Dec 3, 2020
[EMPHASIS] Virtual Launch Event
of EMPHASIS Research Centre
University of Cyprus
In case you missed any parts of the event, the recording can be found at the link below on our YouTube channel:
For more information, please reach out
iezekiel@ucy.ac.cy EMPHASIS Director
Sincerely,
Chrysafis Andreou, PhDLecturerDepartment of Electrical and Computer EngineeringEmphasis Research CentreUniversity of Cyprus
[FOSDEM 2021] Open Source Computer Aided Design and Modeling devroom
We are pleased to announce the CfP for:
Open Source Computer Aided Design and Modeling devroom
at FOSDEM 2021,
on Sunday, 7 February 2021
FOSDEM website:
FOSDEM Code of Conduct:
We hope you'll join us for a full day of talks, demos and interesting discussions on designing, modeling and testing hardware using Open Source tools. This year's event will be fully virtual and will feature multiple channels for talks, Q&A as well as hallway discussions.
We welcome any talk proposals about the creation of physical objects.
Topics of interest include, but are not limited to:
- Open Hardware projects
- Circuit Design
* Printed circuit board design tools
* Circuit simulation
- 3d modeling and analysis
* Solid modeling tools
* Meshing, modeling and transforming physical representations
* Finite element analysis
- 3d printing
* 3d slicing tools
* Motor control
- Machine design and integration
* ECAD/MCAD integration
* Thermal analysis
* Wire modeling
- Physical Model Data storage
* Data representation and optimization
* Version control in hardware data storage
* Collaborative and team-based hardware design techniques
Slots will be allocated for short (20 minutes) and long (40 minutes) talks. Speakers need to specify their preferred format. Both include time for questions and answers. Depending on the number of submissions, submitters may be asked to utilize an alternate time format.
The submission process
* Printed circuit board design tools
* Circuit simulation
- 3d modeling and analysis
* Solid modeling tools
* Meshing, modeling and transforming physical representations
* Finite element analysis
- 3d printing
* 3d slicing tools
* Motor control
- Machine design and integration
* ECAD/MCAD integration
* Thermal analysis
* Wire modeling
- Physical Model Data storage
* Data representation and optimization
* Version control in hardware data storage
* Collaborative and team-based hardware design techniques
Slots will be allocated for short (20 minutes) and long (40 minutes) talks. Speakers need to specify their preferred format. Both include time for questions and answers. Depending on the number of submissions, submitters may be asked to utilize an alternate time format.
The submission process
Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM21
If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one.
Please include the following information with your submission:
https://penta.fosdem.org/submission/FOSDEM21
If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one.
Please include the following information with your submission:
- Abstract- Preferred Session length- Speaker bio- Link to any hardware / code /slides for the talk
When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Open Source Computer Aided Modeling and Design" in the track drop-down menu. Otherwise, your proposal may go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Keep in mind that much of the value in these meetings comes from the discussions, so please allot at least 20% of the talk time for questions and answers.
Important dates
- Call for papers available: 2 December 2020Recordings
- Call for participation closes: 20 December 2020
- Devroom schedule available: 24 December 2020
- Talk recording uploads due: no later then 14 January 2020
- Devroom day: Sunday 7 February 2021 (09:00 to 17:00)
Because this year's conference will be fully virtual, all talks must be pre-recorded. These will be verified for sound and video quality prior to the conference.
Each accepted talk will have a dedicated chaperone to help you through the process of recording, encoding and uploading your talk.
The recordings will be published under the same license as all FOSDEM
content (CC-BY).
content (CC-BY).
open-hardware-devroom@lists.fosdem.org
https://lists.fosdem.org/listinfo/open-hardware-devroom
Dec 2, 2020
Dec 1, 2020
[paper] THz characterization and modeling of SiGe HBTs
Sebastien Fregonese, Marina Deng, IEEE member, Marco Cabbia, Chandan Yadav*, IEEE member, Magali De Matos, and Thomas Zimmer, Senior Member, IEEE
THz characterization and modeling of SiGe HBTs
review (invited)
IEEE J-EDS, 2020, pp.1-1
DOI:10.1109/JEDS.2020.3036135
hal-03014869
IMS Laboratory, University of Bordeaux (F)
*Department of Electronics and Communication Engineering, National Institute of Technology Calicut (IN)
Abstract: This paper presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/deembedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-spice cosimulation that integrates the whole calibration cum deembedding procedure.
Fig: EM probe models based on Picoprobe GGB (a) 1 GHz -110 GHz, (b) WR5, (c) WR3 and d) WR2.2. In all models, white=coaxial insulator, gray=solder, yellow=metal.
A complete description of probe topology and technology is given in:
A. Rumiantsev et R. Doerner; RF Probe Technology: History and Selected Topics; IEEE Microw. Mag., vol. 14, no 7, p. 46‑58, Nov. 2013, DOI: 10.1109/MMM.2013.2280241
Aknowledgement: This work is partly funded by the French Nouvelle-Aquitaine Authorities through the FAST project. The authors also acknowledge financial support from the EU under Project Taranto (No. 737454). The authors would like to thank STM for supplying the silicon wafer.
Nov 30, 2020
[paper] SPICE-level Crossbar-array Circuit Simulator
Fan Zhang1 and Miao Hu2
CCCS: Customized SPICE-level Crossbar-array Circuit Simulator
for In-Memory Computing
IEEE/ACM International Conference on Computer-Aided Design
(ICCAD ’20) November 2– 5, 2020, Virtual Event, USA.
ACM, New York, NY, USA, 8 pages.
DOI: 10.1145/3400302.3415627
1Arizona State University Tempe, Arizona2Binghamton University Binghamton, New York
ABSTRACT: Resistive crossbar arrays are known for their unique structure to implement analog in-memory vector-matrix-multiplications (VMM). However, general-purpose circuit simulators, such as HSPICE and HSIM, are too slow for large scale crossbar array simulations with consideration of circuit parasitics. Although there are some specific simulators designed for crossbar arrays, they mainly focus on area/power/delay estimation rather than accurate SPICE-level simulation, thus could not model its functionality on analog in-memory computing. In this paper, we firstly give a SPICE-level modeling of resistive crossbar array with consideration of circuit parasitics in MATLAB. We also propose efficient methods to further speedup simulations by model simplifications. Last but not least, ResNet-20 on CIFAR-10 is applied to demonstrate the work. With the proposed model simplification methods, simulation speed can be improved by ~31X with tolerable errors, and more than 5X speedup is achieved on ResNet-20 while the accuracy drop is 6%.
Figure: Implement the ResNet on the crossbar with sub-block optimization.
RELATED WORK: Other than general-purpose circuit simulators, specific simulation platforms have been proposed for crossbar-based application analysis; examples include:
[MNSIM] L. Xia, B. Li, T. Tang, P. Gu, X. Yin, W. Huangfu, P. Chen, S. Yu, Y. Cao, Y. Wang, Y. Xie, and H. Yang. MNSIM: Simulation platform for memristor-based neuromorphic computing system. In 2016 Design, Automation Test in Europe Conference Exhibition (DATE). 469–474.
[NeuroSim] P. Chen, X. Peng, and S. Yu. 2018. NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 12 (Dec 2018), 3067–3080.
#Urban Explorers Reveal A #Treasure Trove Of #Soviet #Computing Power
#Urban Explorers Reveal A #Treasure Trove Of #Soviet #Computing Power https://t.co/5dLGxTSMRF#semi
— Wladek Grabinski (@wladek60) November 30, 2020
from Twitter https://twitter.com/wladek60
November 30, 2020 at 07:55PM
via IFTTT
[paper] The advantages of p-GaN channel/Al2O3 gate insulator
Maria Ruzzarin,1, Carlo De Santi,1 Feng Yu,2 Muhammad Fahlesa Fatahilah,2 Klaas Strempel,2 Hutomo Suryo Wasisto,2 Andreas Waag,2 Gaudenzio Meneghesso,1 Enrico Zanoni,1
and Matteo Meneghini1
Highly stable threshold voltage in GaN nanowire FETs: The advantages of p-GaN channel/Al2O3 gate insulator
Appl. Phys. Lett. 117, 203501 (2020);
DOI: 10.1063/5.0027922
Published Online: 16 November 2020
1 Department of Information Engineering, University of Padova, via Gradenigo 6/b, 35131 Padova, Italy
2 Institute of Semiconductor Technology (IHT) and Laboratory for Emerging Nanometrology (LENA), Technische Universitat Braunschweig, Langer Kamp 6a/b, 38106 Braunschweig, Germany
Abstract: We present an extensive investigation of the charge-trapping processes in vertical GaN nanowire FETs with a gate-all-around structure. Two sets of devices were investigated: Gen1 samples have unipolar (n-type) epitaxy, whereas Gen2 samples have a p-doped channel and an n-p-n gate stack. From experimental results, we demonstrate the superior performance of the transistor structure with a p-GaN channel/Al2O3 gate insulator in terms of dc performance. In addition, we demonstrate that Gen2 devices have highly stable threshold voltage, thus representing ideal devices for power electronic applications. Insight into the trapping processes in the two generations of devices was obtained by modeling the threshold voltage variations via differential rate equations.
Fig. a) The p-channel device (Gen2) comprises a 2.5 lm n-GaN buffer layer, a 0.5 lm p-GaN channel layer, 0.73 lm n-GaN and 0.5 lm n p-GaN as the top layer, and 25 nm-Al2O3 as the gate dielectric.
b) SEM images of a nanowire of the p-channel device (Gen2) and bird’s-eye view of vertically aligned n-p-n GaN nanowire (NW) arrays with top contacts.
Aknowledgement: This work was supported in part by NoveGaN (Univ. of Padova) through the STARS CoG Grants call. Ack prog. Eccellenza. This research was partly performed within project INTERNET OF THINGS: SVILUPPI METODOLOGICI, TECNOLOGICI E APPLICATIVI and co-funded (2018–2022) by the Italian Ministry of Education, Universities and Research (MIUR) under the aegis of the “Fondo per il finanziamento dei dipartimenti universitari di eccellenza” initiative (Law 232/2016). Financial support from the German Research Foundation (DFG) of 3D GaN project and the Lower Saxony Ministry of Science and Culture (N-MWK) of LENA-OptoSense group is highly acknowledged for the development of vertical GaN nanowire FETs.
Nov 29, 2020
#top10 Hottest Semiconductor #Startups Of #2020
#top10 Hottest Semiconductor #Startups Of #2020 https://t.co/wIJrk3NU6b #semi
— Wladek Grabinski (@wladek60) November 29, 2020
from Twitter https://twitter.com/wladek60
November 29, 2020 at 08:50PM
via IFTTT
Nov 28, 2020
[paper] How Objective is Peer Review?
By Hannah Bast
November 18, 2020
In 2014, the organizers of the Conference on Neural Information Processing Systems (NeurIPS, then still called NIPS) made an interesting experiment.1 They split their program committee (PC) in two and let each half independently review a bit more than half of the submissions. That way, 10% of all submissions (166 papers) were reviewed by two independent PCs. The aimed at acceptance rate per PC was 23%. The result of the experiment was that among these 166 papers, the set of accepted papers from the two PCs overlapped by only 43%. That is, more than half of the papers accepted by one PC were rejected by the other. This led to a passionate flare-up of the old debate of how effective or random peer-reviewing really is and what we should do about it. [read more...]
My bottom line: The reputation of the peer review process is tarnished. Let us work on this with the same love and attention we give to our favorite research problems. Let us do more experiments to gain insights that help us make the process more fair and regain some trust. And let us create powerful incentives, so that whatever we already know is good is actually implemented and carried over from one PC to the next.
References:
1 https://cacm.acm.org/blogs/blog-cacm/181996-the-nips-experiment provides a short description of the NIPS experiment and various links to further analyses and discussions.
2 https://github.com/ad-freiburg/esa2018-experiment
3 There are other experiments, like the single-blind vs. double-blind experiment at WSDM'17, which investigated a particular aspect of the reviewing process: https://arxiv.org/abs/1702.00502
Nov 27, 2020
#Brazilian Senate approves #tax exemption for #IoT devices
#Brazilian Senate approves #tax exemption for #IoT devices | ZDNet https://t.co/TYKRem4tcR#semi
— Wladek Grabinski (@wladek60) November 27, 2020
from Twitter https://twitter.com/wladek60
November 27, 2020 at 05:40PM
via IFTTT
£20m for Turing Fellowships
£20m for Turing Fellowships:
New Turing #AI Acceleration #Fellowships will give fifteen of the UK’s top AI innovators the resources to drive forward research from speeding up medical diagnosis to increasing workplace productivity. https://t.co/9nIjr67rwE#semi pic.twitter.com/9opCVAFWGi
— Wladek Grabinski (@wladek60) November 27, 2020
from Twitter https://twitter.com/wladek60
November 27, 2020 at 03:26PM
via IFTTT
[paper] Trillion-transistor chip breaks speed record
Kamil Rocki∗, Dirk Van Essendelft†, Ilya Sharapov∗, Robert Schreiber∗, Michael Morrison∗, Vladimir Kibardin∗, Andrey Portnoy∗, Jean Francois Dietiker†‡, Madhava Syamlal†
and Michael James∗
Fast Stencil-Code Computation on a Wafer-Scale Processor
Online SC20 Supercomputing Conference
arXiv:2010.03660 [cs.DC] (2020)
∗ Cerebras Systems Inc., Los Altos, California, USA
† National Energy Technology Laboratory, Morgantown, West Virginia, USA
‡ Leidos Research Support Team, Pittsburgh, Pennsylvania, USA
Abstract: The performance of CPU-based and GPUbased systems is often low for PDE codes, where large, sparse, and often structured systems of linear equations must be solved. Iterative solvers are limited by data movement, both between caches and memory and between nodes. Here we describe the solution of such systems of equations on the Cerebras Systems CS-1, a wafer-scale processor that has the memory bandwidth and communication latency to perform well. We achieve 0.86 PFLOPS on a single wafer-scale system for the solution by BiCGStab of a linear system arising from a 7-point finite difference stencil on a 600 × 595 × 1536 mesh, achieving about one third of the machine’s peak performance. We explain the system, its architecture and programming, and its performance on this problem and related problems. We discuss issues of memory capacity and floating point precision. We outline plans to extend this work towards full applications.
Fig: CS-1 Wafer Scale Engine (WSE). A single wafer (rightmost) contains one CS-1 processor. Each processor is a collection of dies arranged in a 2D fashion (middle). Dies are then further subdivided into a grid of tiles. One die hosts thousands of computational cores, memory and routers (leftmost). There is no logical discontinuity between adjacent dies and there is no additional bandwidth penalty for crossing the die-die barrier. In total, there are 1.2 trillion transistors in an area of 462.25 cm2.
Acknowledgement: The authors would like to thank Natalia Vassilieva for initiating the collaboration between Cerebras Systems and NETL and for her subsequent help with the project.
Nov 26, 2020
[book] MEMS Fundamentals
MEMS Fundamentals
with ANSYS simulation of basic sensors and actuators
Michał Szermer, Andrzej Napieralski (Eds.)
ISBN eBook: 978-83-66287-64-8, 9788366287648
Wydawnictwo Politechniki Łódzkiej
Intro: The purpose of this book is to help universities and individuals extend their traditional microelectronics education into the MEMS area. It is organized in a set of tutorials primarily aimed at electronic engineering students and practicing engineers. Based on carefully selected examples of sensors and actuators, it introduces the reader to device operating principles, modeling approaches, simulation tools and design methodologies.
Book Contents
PrefaceChapter 1. INTRODUCTION
1.1. Program description
1.2. References
Chapter 2. SILICON MEMBRANE
2.1. Introduction
2.2. Modeling
2.2.1. Getting started
2.2.2. Setting system of units
2.2.3. Selecting finite element types
2.2.4. Setting material properties
2.2.5. Defining geometry
2.2.6. Meshing
2.2.7. Selecting analysis type
2.2.8. Applying boundary conditions
2.2.9. Running analysis
2.2.10. Viewing simulation results
2.3. Tasks for students
2.4. References
Chapter 3. THERMAL ACTUATOR
3.1. Introduction
3.2. Modeling
3.2.1. Getting started
3.2.2. Defining geometry
3.2.3. Setting material properties
3.2.4. Setting finite element types
3.2.5. Meshing
3.2.6. Selecting analysis type
3.2.7. Applying boundary conditions
3.2.8. Running analysis
3.2.9. Viewing simulation results
3.3. Automation of MEMS thermal actuator design
3.3.1. Simulation of thermal actuator with varying heater temperature
3.3.2. Viewing and saving simulation results using POST1 postprocessor
3.3.3. Plotting relationships
3.3.4. Tasks for students
3.4. References
Chapter 4. ELECTROTHERMAL ACTUATOR
4.1. Introduction
4.2. Modeling
4.2.1. Getting started
4.2.2. Defining geometry
4.2.3. Setting finite element types
4.2.4. Setting material properties
4.2.5. Meshing
4.2.6. Applying boundary conditions
4.2.6.1. Clamp
4.2.6.2. Temperature
4.2.6.3. Voltage
4.2.7. Selecting analysis type
4.2.8. Running analysis
4.2.9. Viewing simulation results
4.2.9.1. Displacement
4.2.9.2. Voltage
4.2.9.3. Temperature
4.3. Tasks for students
4.4. References
Chapter 5. ACCELEROMETER
5.1. Introduction
5.2. Modeling
5.2.1. Getting started
5.2.2. Defining geometry
5.2.3. Setting finite element types
5.2.4. Setting material properties
5.2.5. Meshing
5.2.6. Applying boundary conditions
5.2.7. Selecting analysis type
5.2.8. Running analysis
5.2.9. Viewing simulation results
5.3. Tasks for students
5.4. References
Chapter 6. SILICON MEMBRANE IN WORKBENCH
6.1. Membranes
6.2. Membrane modeling
6.3. Design and modeling of the membrane
6.3.1. Introduction to ANSYS
6.3.2. Getting started
6.3.3. Defining geometry
6.3.4. Setting up the simulation
6.3.5. Results processing
6.4. Exercises for Students
6.4.1. Laboratory tasks
6.4.2. Individual tasks
6.5. References
Chapter 7. MICROBOLOMETER IN WORKBENCH
7.1. Microbolometer principle
7.2. Microbolometer design with ANSYS Workbench
7.2.1. Getting started
7.2.2. Defining geometry
7.2.3. Adding materials’ data to the project
7.2.4. Electrical simulation
7.2.5. Thermal simulation
7.2.6. Exercises for students
7.2.7. Transient thermal simulation
7.2.8. Exercises for students
7.3. References
Nov 25, 2020
[GUEST EDITORIAL] Women in Circuits
GUEST EDITORIAL
Zeynep Toprak-Deniz
Women in Circuits
IEEE SOLID-STATE CIRCUITS MAGAZINE FALL 2020
DOI 10.1109/MSSC.2020.3021864 (18 November 2020)
The “Rising to the Top in Industry” career panel touched upon topics including mentoring, setting career goals, filing patents, and management versus technical tracks.
At the 2020 International Solid-State Circuits Conference (ISSCC), the Women in Circuits (WiC) Committee hosted the first-ever Rising Stars workshop for graduate and undergraduate students as well as young professionals who have graduated within the last two years and are interested in learning how to excel in academic and industry careers in computer science and electrical engineering. Twenty individuals were selected to attend a special dinner featuring a keynote speech by Prof. Anantha P. Chandrakasan - already a risen star - and a mentoring session with committee members. The event also included two panels. The “Rising to the Top in Industry” career panel touched upon topics including mentoring, setting career goals, filing patents, and management versus technical tracks. The “Navigating the Assistant Professorship” panel addressed topics related to applying for a faculty position, tenure review, and managing day-to-day life in academia. The panels were open to all ISSCC 2020 attendees and the public and attracted more than 300 participants. This Fall 2020 issue of IEEE SolidState Circuits Magazine on WiC follows the tradition of previous issues since 2017, enabling more exposure to female leaders through exposition of their work in circuits on a variety of important topics. The following IEEE Solid-State Circuits Society members were asked to contribute tutorials for this issue:
- Jane Gu, associate professor at the University of California, Davis, and member of the Technical Program Committee (TPC) for the IEEE Radio Frequency Integrated Circuits Symposium, Custom Integrated Circuits Conference (CICC), and ISSCC, is an associate editor of IEEE Microwave and Wireless Components Letters and VLSI Journal of Integration and guest editor of IEEE Journal of Solid-State Circuits (JSSC).
- Ulkuhan Guler, assistant professor at Worcester Polytechnic Institute, is a senior member of JSSC and serves on the CICC TPC.
- Alicia Klinefelter, senior research scientist in the ASIC and VLSI research group at NVIDIA, has served on the ISSCC TPC since 2018.
- Yan Li, vice president for memory design at Western Digital, leading the design of advanced 3D NAND as well as other nonvolatile memories and new innovation initiatives, serves on the ISSCC Machine Learning TPC.
- Rabia Yazicigil, assistant professor in the Department of Electrical and Computer Engineering at Boston University and visiting scholar at the Massachusetts Institute of Technology, was vice-chair of the 2020 Rising Stars workshop.
- Maneesha Yellepeddi, manager of the Programmable Solutions Group at Intel, is an alumnus of the 2020 Rising Stars workshop.
ISSCC 2021 will continue this tradition by hosting another Sunday evening workshop bringing together experts in cloud-connected biosensors, advance algorithms, and artificial intelligence to discuss our preparedness for combating the spread of infectious diseases now and in the future. The “ICs in PandemICs” panel will feature recent work on remote patient monitoring and data analysis with related security and privacy concerns. I hope to see you all there!
Fwd: Online Skill Enhancement Program for SCIENCE Students to be held during December 02 - 08, 2020 from 05:00 pm - 06:30 pm daily.
On behalf of the DBT Star College Program and Department of Electronics
We invite all FIRST AND SECOND Year science students of your institution to join
the Online Skill Enhancement Program
to be held during
December 02 - 08, 2020 from 05:00 pm - 06:30 pm daily
Kindly register via Zoom Link No Registration Fees:
https://us02web.zoom.us/webinar/register/WN_gug93-ABQr-IoAGdW_juoQ
The objective of the program is to make the students first feel comfortable in their new environment, open them up, create bonding and to connect, learn new things about sensors, mechanics, control, programming the microcontroller to see how it works and controls various aspects be they of biology, zoology, chemistry, physics, mathematics or computers. So this workshop will be useful for all science students to help them explore their knowledge in their fields as well as other fields. Today there is a need to take the concepts of various fields together. This is to skill them in the basic concepts of programming the robotic and control aspects of various applications and sensitize them towards exploring their academic interest and activities.
This program will provide an opportunity for all the science stream students to get some experience in the new way and enhance their knowledge towards interdisciplinary learning. All students having a passion to learn and explore a new world of automation and control and start experimenting with robotic applications are most welcome to participate.
Organizing Committee
Dr. Poonam Kasturi
The objective of the program is to make the students first feel comfortable in their new environment, open them up, create bonding and to connect, learn new things about sensors, mechanics, control, programming the microcontroller to see how it works and controls various aspects be they of biology, zoology, chemistry, physics, mathematics or computers. So this workshop will be useful for all science students to help them explore their knowledge in their fields as well as other fields. Today there is a need to take the concepts of various fields together. This is to skill them in the basic concepts of programming the robotic and control aspects of various applications and sensitize them towards exploring their academic interest and activities.
This program will provide an opportunity for all the science stream students to get some experience in the new way and enhance their knowledge towards interdisciplinary learning. All students having a passion to learn and explore a new world of automation and control and start experimenting with robotic applications are most welcome to participate.
Kindly register via Zoom Link: https://us02web.zoom.us/webinar/register/WN_gug93-ABQr-IoAGdW_juoQ
Organizing Committee
Dr. Poonam Kasturi
Convener-DBT Star College Program (Electronics)Teacher-in-Charge, Department of ElectronicsDeen Dayal Upadhyaya CollegeUniversity of Delhi
Dr. Manoj Saxena | डॉ मनोज सक्सेना
Program Coordinator - DBT Star College Program (DDUC)Associate Professor | सह - आचार्यDepartment of Electronics | इलेक्ट्रॉनिक्स विभागDeen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेजUniversity of Delhi | दिल्ली विश्वविद्यालयDwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८India | भारत
Nov 24, 2020
[paper] Compact Models for Sizing Based on ANN
Husni Habal, Dobroslav Tsonev, Matthias Schweikardt
Compact Models for Initial MOSFET Sizing Based on Higher-order Artificial Neural Networks
ACM/IEEE Workshop on Machine Learning for CAD (MLCAD ’20)
Nov. 16–20, 2020, Virtual Event, Iceland. ACM, pp. 111-116
DOI: 10.1145/3380446.3430632
1Infineon Technologies AG Munich, Germany
2LogiqWorks Ltd. Sofia, Bulgaria
3Reutlingen University Reutlingen, Germany
2LogiqWorks Ltd. Sofia, Bulgaria
3Reutlingen University Reutlingen, Germany
Abstract: Simple MOSFET models intended for hand analysis are inaccurate in deep sub-micrometer process technologies and in the moderate inversion region of device operation. Accurate models, such as BSIM6 model, are too complex for use in hand analysis and are intended for circuit simulators. Artificial neural networks (ANNs) are efficient at capturing both linear and non-linear multivariate relationships. In this work, a straightforward modeling technique is presented using ANNs to replace the BSIM model equations. Existing open-source libraries are used to quickly build models with error rates generally below 3%. When combined with a novel approach, such as the gm/Id systematic design method, the presented models are sufficiently accurate for use in the initial sizing of analog circuit components without simulation.
Figure: ANN Model Architecture.
Nov 23, 2020
[paper] Noise Modeling of Gate Leakage Current in Nanoscale MOSFETs
Jonghwan Lee*
Noise Modeling of Gate Leakage Current in Nanoscale MOSFETs
Journal of the Semiconductor & Display Technology,
Vol. 19, No. 3. September 2020
*Department of System Semiconductor Engineering, Sangmyung University
Abstract: The physics-based compact gate leakage current noise models in nanoscale MOSFETs are developed in such a way that the models incorporate important physical effects and are suitable for circuit simulators, including QM (quantummechanical) effects. An emphasis on the trap-related parameters of noise models is laid to make the models adaptable to the variations in different process technologies and to make its parameters easily extractable from measured data. With the help of an accurate and generally applicable compact noise models, the compact noise models are successfully implemented into BSIM (Berkeley Short-channel IGFET Model) format. It is shown that the noise models have good agreement with measurements over the frequency, gate-source and drain-source bias ranges.
Fig: Implementation of the gate leakage current and noise
models into the BSIM model
Input deck to simulate MOSFET Noise*m1 2 1 0 0 mod1 L=10u W=10u*vgs 1 0 dc 1.4 ac 1vds 3 0 dc 0.3rdd 2 3 1*.include model.TI_nmos.op.dc vgs 1 5 0.5.print dc igd(vgs)*.ac dec 10 1 100Meq.noise v(2) vgs dec 10 1 100Meg 1.plot noise onoisa inoise*.end
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