[FOSSi] OpenLANE: Open Source 130nm PDK

Join Mohamed Shalan for the 2nd talk in the Free and Open Source Silicon (FOSSi) Foundation Dial-Up series is on Tuesday 28th July, he will talk about OpenLANE on the first-in-the-industry Open Source Manufacturable SkyWater 130nm PDK

Mohamed Shalan - OpenROAD on SkyWater 130nm

Unlike the wider software world, Electronic Design Automation (EDA) open-source landscape has been fragmented for a long time, requiring significant effort and knowledge in a variety of disciplines to assemble a working ASIC flow. This has changed with projects such as Qflow and OpenROAD that aim at developing open-source toolchain for digital layout generation from RTL. OpenLane is an automated RTL to GDSII flow based on available opensource EDA tools configured/tuned for the SkyWater 130nm PDK. OpenLane main objective is to generate a clean layout from RTL designs in less than 24-hours with zero human interventions. OpenLane has been used, successfully, to tape-out a family of test chips (striVe).

Join live on YouTube on Tuesday July 28 at 16:00GMT https://lnkd.in/gCyMuPp

[paper] Vectorizing Device Model Evaluation in Ngspice

Vectorizing Device Model Evaluation in Ngspice circuit simulator

Florian Ballenegger, Anamosic Ballenegger Design

Preprint July 2020

Abstract: A method improving the execution speed of electrical circuit simulation using vector processing is proposed. The BSIM3V32 semi-conductor device model for the open-source Ngspice simulator has been re-written for evaluating multiple device instances of the same model at once using Single Instruction Multiple Data (SIMD) processor instructions. While parallel evaluation of device model was already available using multiprocessing, the proposed method can achieve the same speed-up using less processor resources, thus allowing to do more parallel independent simulations for statistical analysis.

In Conclusion: Only the BSIM3V32 device model was modified to use vector processing. Other device models would of course also benefit from the proposed method. In particular interest would be the EKV model https://github.com/ekv26/model, as the calculations in this symmetric model are more linear with fewer conditional branches and could be vectorized more efficently.  The source code of the modified BSIM3V3 model is available at https://www.anamosic.com/pages/ngspice.html

Softbank talks to #Apple and #Nvidia about #Arm sale https://t.co/pgShLwpAz1 #semi https://t.co/KOS9UIIhO1

Softbank talks to #Apple and #Nvidia about #Arm sale https://t.co/pgShLwpAz1 #semi pic.twitter.com/KOS9UIIhO1

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U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ #semi https://t.co/Zxeyxds702

U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ#semi pic.twitter.com/Zxeyxds702

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#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O #paper

#Intel conceding the battle to #ARM and #AMD as 7nm processors delayed even further https://t.co/FHOPn7AA0O#paper

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[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.

[paper] Compact Model of All-Optical-Switching Magnetic Elements

J. Pelloux-Prayer¹ and F. Moradi¹

Compact Model of All-Optical-Switching Magnetic Elements

IEEE TED, vol. 67, no. 7, pp. 2960-2965, July 2020

DOI: 10.1109/TED.2020.2991330.

¹Department of Engineering, Aarhus University, 8200 Aarhus, Denmark

Abstract: We present, for the first time, a Verilog-A compact model for an all-optically switchable magnetic tunnel junction (MTJ) using results of all-optical-switching (AOS) simulations. Our model is compatible with electronics and photonics design automation tools, and was tested using Cadence Specter and Virtuoso. This compact model can be used to design circuits and systems combining MTJs, photonic circuits, and electronic circuits giving the possibility to researchers working within this field to develop novel circuits and systems.

Fig: Equivalent circuit of the AOS model with LLGS module and LUT module.

Aknowledgement: This work was supported by the European Union’s Horizon 2020 Research and Innovation Programme under Grant 713481.

[paper] LF Noise Characterization of Ge n-Channel FinFETs

Alberto V. de Oliveira (Member, IEEE), Duan Xie (Member, IEEE), Hiroaki Arimura, Guillaume Boccardi, Nadine Collaert, Cor Claeys (Fellow, IEEE), Naoto Horiguchi (Member, IEEE)

and Eddy Simoen (Senior Member, IEEE_

Low-Frequency Noise Characterization of Germanium n-Channel FinFETs

IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2872-2877, July 2020

DOI: 10.1109/TED.2020.2990714

Abstract: This article presents an experimental, room temperature, low-frequency noise characterization of germanium n-channel fin-field-effect transistors (finFETs) integrated on silicon. After determining the dominant mechanism in the noise spectrum, the main parameters associated with the noise mechanism are extracted and evaluated as a function of fin width from a planar-like (100 nm) up to narrow fin (20 nm) for 1-µm length devices. The main findings are that the 1/f noise plays an important role in the Ge n-finFETs, whereby the trap density profiles in the gate-stack are quite uniform and have a lower level than in n-/p-channel Ge planar MOSFETs. In addition, a generation-recombination (GR) component was found in 160-nm-length devices, which is caused by GR centers located in the depletion region.

Fig: (a) Schematic of the Ge  n-finFET structure 

and (b) gate-stack composition

Fig: Drain current noise power spectral density as a function of frequency 

for a 160nm long Ge n-finFET

Acknowledgment: The authors would like to thank the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) and the Logic IIAP program for the support. This work has been performed in the frame of the imec Core Partner program on Ge devices.

[paper] Thyristor Conduction-Insulated Gate Bipolar Transistor

Mengxuan Jiang¹ (Member, IEEE) and Longjiang Gao¹

Simulation Study of a Thyristor Conduction-Insulated Gate Bipolar Transistor (TC-IGBT) 

with a p-n-p Base and an n-p-n Collector for Reducing Turn-Off Loss," 

IEEE TED, vol. 67, no. 7, pp. 2854-2858, July 2020

DOI: 10.1109/TED.2020.2995343

¹School of Electrical Engineering, Chongqing University, Chongqing 400044, China

Abstract: This article proposes a thyristor conduction-insulated gate bipolar transistor (TC-IGBT) with a p-n-p base and an n-p-n collector to reduce turn-off loss. The parasitic p-collector/n-drift/floating p (FP)-layer/carrier stored (CS)-layer thyristor is activated by the double channel gate and the p-n-p base acts a hole barrier to increase hole concentration at the top side. The n-p-n collector is used for extracting electrons from the n-drift region to decrease hole concentration at the bottom side. Therefore, these two effects form linear and descending hole concentration distribution profile. As a result, the p-n-p base and the n-p-n collector in the TC-IGBT offers lower turn-off loss and turn-off fall time. TCAD numerical simulations show reductions up to 47% (3.15 mJ) and 52% (34 ns) in turn-off loss and turn-off fall time, respectively, when compared to a field stop (FS) IGBT with similar breakdown voltage, threshold voltage, and short circuit time. Therefore, this designed structure may be attractive for power electronics applications.

Fig: (a) Proposed TC-IGBT and (b) its equivalent circuit model

Acknowledgment: This work was supported in part by the National Natural Science Foundation of China under Grant 51707025 and in part by the Chinese Universities Scientific Fund under Grant 106112017 CDJXY150099.

[paper] Unified Analytical Model for SOI LDMOS

Baoxing Duan, Jingyu Xing, Ziming Dong and Yintang Yang¹ (Senior Member, IEEE)

Unified Analytical Model for SOI LDMOS With Electric Field Modulation

IEEE J-EDS, vol. 8, pp. 686-694, 2020

DOI: 10.1109/JEDS.2020.3006293

¹Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi’an 710071, China

Abstract: The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates the surface electric field by the electric field modulation effect to optimize the surface electric field distribution of the device. Also, the simulation results obtained through the simulation software ISE are consistent with the expected results of the analytical model. This not only proves the feasibility of the electric field modulation theory, but also shows that the accurate analytical model will be of great guiding significance for designing and optimizing the same LDMOS based on SOI structures.

FIG: Cross-sectional view of electric field modulated SOI LDMOS

Acknowledgment: This work was supported in part by Science Foundation for Distinguished Young Scholars of Shaanxi Province under Grant 2018JC-017, and in part by the 111 Project under Grant B12026.

Fwd: IEEE-EDS SCV/SF Chapter July Distinguished Lecture (Webex only)

Dear IEEE EDS members in Santa Clara Valley/San Francisco Chapter

Please note that this seminar is now WEBEX participation only. 

Differentiated Fully Depleted SOI (FDSOI) Technology for Highly Efficient and Integrated mmWave Wireless Connectivity Solution

Speaker: Dr. Anirban Bandyopadhyay, Director, Strategic Marketing and Business Analytics, GLOBALFOUNDRIES, Inc., Santa Clara, CA

Friday, July 24, 2020 at 12PM – 1PM PDT

WEBEX ONLY: Click Here to Attend

Abstract:

The emergence of enhanced mobile broadband (eMBB) connectivity based on mmWave 5G and the emerging prospect of broadband internet to using non-terrestrial mmwave backhaul using low earth orbit (LEO) satellite generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage, generating enough transmitted power efficiently particularly in the uplink, system cost & scaling and long term reliability of the hardware system particularly for infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmWave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits.

Speaker Bio:

Dr. Anirban Bandyopadhyay is the Director, Strategic Marketing and Business Analytics within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmWave applications. Prior to joining GLOBALFOUNDRIES, he was with IBM Microelectronics, New York and with Intel, California where he worked on different areas like RF Design Enablement, Silicon Photonics, signal integrity in RF & Mixed signal SOC's. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research, India and Post-Doctoral research at Nortel, Canada and at Oregon State University, USA. He represents Global Foundries in different industry consortia on RF/mmWave applications and is a Distinguished Lecturer of IEEE Electron Devices Society.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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[C4P] Advanced FETs: Design, Fabrication and Applications

Call for Papers: Special MDPI  Issue 

"Advanced Field Effect Transistors: Design, Fabrication and Applications"

Deadline for manuscript submissions: 31 July 2021.

Dear Colleagues,

Planar MOS Field Effect Transistors (MOSFETs) were invented by Atalla and Kahng in 1959. After a decade, the MOSFETs entered mass production, as basic building blocks of P-, N-, and CMOS integrated circuits (ICs). Until the end of the twentieth century, MOSFET performance was largely improved by the implementation of so-called scaling rules. An exponential growth in the time of the transistor number per chip (observation formulated as Moore law) was achieved. This, together with advantageous characteristics and a nice feature of the planar MOSFETs allowing one to design the ICs by defining a width/length ratio, led to the great success of the CMOS technology on Si and SOI substrates.

However, starting from the 90 nm node, it has been observed that the standard scaling does not sufficiently translate into MOSFET performance improvement. Moreover, some device characteristics become degraded, e.g. gate leakage, channel leakage, variability and reliability. This has led to the development of preventative measures (e.g. high-k dielectrics) or performance boosters (e.g. channel strain engineering and channel materials). Furthermore, 2D and 3D multi-gate FETs were introduced to improve gate control over the channel and increase the channel aspect ratio. Multi-gate FETs are the only option for the 5nm node, which is expected soon, whereas they will have to be replaced by surrounding gate FETs for the 3nm node. For the past few years, the attention of researchers has been attracted by steep-subthreshold slope devices, enabling the reduction of supply voltage. A need for devices for quantum computing has appeared. FETs and HEMTs, for very high frequency applications, GaN, SiC and FETs for high voltage, high power, high temperature applications, and many other FET types, are in use or under development as a micro- and nanoelectronics reply to electronics needs in different domains.

There are many issues regarding the design, fabrication and applications of advanced field effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications and reviews are all welcome.

Dr. Daniel Tomaszewski, ITE, Warsaw (PL)
Special Issue Guest Editor

[read more...]

#Free #software is what unites us [Free Software Foundation] https://t.co/EMNQwbkn5Q #opensource https://t.co/oLachje3z4

#Free #software is what unites us [Free Software Foundation] https://t.co/EMNQwbkn5Q#opensource pic.twitter.com/oLachje3z4

— Wladek Grabinski (@wladek60) July 17, 2020

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July 17, 2020 at 06:25PM
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[paper] Compact Modeling of NC FDSOI FETs

C. K. Dabhi, S. S. Parihar, A. Dasgupta and Y. S. Chauhan

Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations

IEEE TED, vol. 67, no. 7, pp. 2710-2716, July 2020

DOI: 10.1109/TED.2020.2994018

Abstract: The compact model for negative capacitance FDSOI (NC-FDSOI) FET with metal–ferroelectric–insulator– semiconductor (MFIS) gate-stack is presented, for the first time, in this article. The model is developed based on the framework of BSIM-IMG, an industry-standard model (i.e., for zero thickness of a ferroelectric layer, the model mimics the behavior of BSIM-IMG). The developed NCFDSOI model is computationallyefficient and captures drain current and its derivatives accurately. The model shows an excellent agreement with numerical simulation and the measured data of NC-FDSOI FET. The proposed compact model is implemented in Verilog-A and tested for circuit simulations using commercial circuit simulators.

Fig: (a) Schematic of NC MFIS FDSOI FET - FE layer is sandwiched between the oxide layer and the top gate. (b) Gate-stack of MFIS FDSOI FET. (c) Gate-stack of MFMIS FDSOI FET.

Acknowledgment: This work was supported in part by the Swarnajayanti Fellowship and FIST Scheme of the Department of Science and Technology and in part by the Berkeley Device Modeling Center (BDMC). The authors would like to thank Dr. Sarvesh S. Chauhan for reading the manuscript and providing valuable feedback.

[paper] FD-SOI CMOS RF FoM

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

Lucas Nyssens¹ (Graduate Student Member, IEEE), Arka Halder¹, Babak Kazemi Esfeh¹,
Nicolas Planes², Denis Flandre¹ (Senior Member, IEEE), Valeriya Kilchytska¹
and Jean-Pierre Raskin¹ (Fellow, IEEE)
IEEE J-EDS, vol. 8, pp. 646-654, 2020,
DOI: 10.1109/JEDS.2020.3002201

¹UCL, 1348 Louvain-la-Neuve (B) ²ST-Microelectronics, 38920 Crolles (F)

Abstract: This work presents a detailed RF characterization of 28nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (f_T) and maximum oscillation frequency (f_max), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ∼130GHz in f_T and ∼75GHz in f_max is observed for the shortest device (25nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2K and clarifies the origin and limitations of the performance.

FIG: Small-signal equivalent circuit of the RF MOSFETs

Aknowledgement: This work was supported in part by Eniac “Places2Be” and in part by Ecsel “Waytogofast” Projects. The work of Lucas Nyssens was supported by the Fonds de la Recherche Scientifique - FNRS. This paper is based on a paper entitled “28 FDSOI RF Figures of Merit Down to 4.2 K,” presented at the 2019 IEEE S3S Conference.

[FOSSi] #Free #chips courtesy of Google, SkyWater, eFabless https://t.co/sZOyCTuty4 #paper https://t.co/xqwS9nl3Ir

[FOSSi] #Free #chips courtesy of Google, SkyWater, eFabless https://t.co/sZOyCTuty4#paper pic.twitter.com/xqwS9nl3Ir

— Wladek Grabinski (@wladek60) July 16, 2020

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[paper] Power Side-Channel Attacks in NCFET

Knechtel, Johann, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf,

Yogesh S. Chauhan, Jörg Henkel, Ozgur Sinanoglu, and Hussam Amrouch

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)

IEEE Micro, DOI 10.1109/MM.2020.3005883

Preprint arXiv:2007.03987 (2020)

Abstract: Side-channel attacks have empowered bypassing of cryptographic components in circuits. Power side-channel (PSC) attacks have received particular traction, owing to their non-invasiveness and proven effectiveness. Aside from prior art focused on conventional technologies, this is the first work to investigate the emerging Negative Capacitance Transistor (NCFET) technology in the context of PSC attacks. We implement a CAD flow for PSC evaluation at design-time. It leverages industry-standard design tools, while also employing the widely-accepted correlation power analysis (CPA) attack. Using standard-cell libraries based on the 7nm FinFET technology for NCFET and its counterpart CMOS setup, our evaluation reveals that NCFET-based circuits are more resilient to the classical CPA attack, due to the considerable effect of negative capacitance on the switching power. We also demonstrate that the thicker the ferroelectric layer, the higher the resiliency of the NCFET-based circuit, which opens new doors for optimization and trade-offs.

Fig: (a) NCFET structure,with ferroelectric layer integrated inside the transistor’s gate stack;

(b) Equivalent caps series, where the internal voltage exhibits a greater voltage (V_int  > V_G)

Acknowledgments: This work was supported in part by the Center for Cyber Security (CCS) at New York University Abu Dhabi (NYUAD). The work of Satwik Patnaik was supported by the Global Ph.D. Fellowship at NYU/NYUAD. Besides, parts of this work were carried out on the HPC facility at NYUAD.

A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv #paper https://t.co/ZNrvrJN0Zd

A Cambridge post-graduate student, Marian Rejewski rebuilds Polish Enigma-code-breaking box that paved the way for Turing ... and Victory! https://t.co/hPLDTC9Ocv#paper pic.twitter.com/ZNrvrJN0Zd

— Wladek Grabinski (@wladek60) July 15, 2020

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July 15, 2020 at 02:21PM
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[paper] First Principles Based Compact Model for 2D-Channel MOSFETs

Das, Biswapriyo, and Santanu Mahapatra

First Principles Based Compact Model for 2D-Channel MOSFETs

researchgate.net online publication

Abstract: We propose a generalized compact model for any two-dimensional material channel-based metal-oxide-semiconductor field-effect transistors. Unlike existing ones, the proposed model is first principles based and thus has ability to predict the circuit performance only using the crystallographic information of the channel material. It is ‘core’ in nature and developed following the industry-standard drift-diffusion formalism based ‘top-down’ hierarchy employing the FermiDirac statistics. We also implement the model in professional circuit simulator and good convergence is observed in 15-stage ring oscillator simulation.

Fig: Synopsis of the modeling framework. First, certain material specific parameters are extracted employing density functional theory computations and Hamiltonian calibration, which thereafter are used to develop the compact device model of the 2D-channel MOSFET using drift-diffusion formalism. The drain current and terminal charges obtained henceforth are used to implement digital circuits in commercial circuit simulator using its Verilog-AMS interface. 

[read more...]

[RG] research paper reached 500 citations

FOSS EKV2.6 Verilog-A Compact MOSFET Model

Wladek Grabinski¹, Marcelo Pavanello², Michelly de Souza², Daniel Tomaszewski³, Jola Malesinska³, Grzegorz Głuszko³, Matthias Bucher⁴, Nikolaos Makris⁴, Aristeidis Nikolaou⁴, Ahmed Abo-Elhadid⁵, Marek Mierzwinski⁶, Laurent Lemaitre⁷, Mike Brinson⁸, Christophe Lallement⁹, Jean-Michel Sallese¹⁰, Sadayuki Yoshitomi¹¹, Paul Malisse¹², Henri Oguey¹³, Stefan Cserveny¹³, Christian Enz¹⁰, François Krummenacher¹⁰ and Eric Vittoz¹⁰ 

in 49th European Solid-State Device Research Conference 

(ESSDERC; pp. 190-193)

DOI: 10.1109/essderc.2019.8901822 

FOSS EKV2.6 Verilog-A at GitHub https://github.com/ekv26/model

¹ MOS-AK Association (EU), 
² Centro Universitario FEI, Sao Bernardo do Campo (BR), 
³ Institute of Electron Technology, Warsaw (PL), 
⁴ Technical University of Crete, Chania (GR), 
⁵ Mentor Graphics (USA), 
⁶ Keysight Technologies (USA), 
⁷ Lemaitre EDA Consulting, 
⁸ London Metropolitan University (UK), 
⁹ ICube, Strasbourg University (F), 
¹⁰ EPFL Lausanne, 
¹¹ Toshiba (J), 
¹² Europractice/IMEC (B), 
¹³ CSEM S.A., Neuchatel (CH)

[paper] Carbon Nanotube Detectors and Spectrometers for the Terahertz Range

Junsung Park¹, Xueqing Liu¹, Trond Ytterdal²

and Michael Shur^1,3 

Carbon Nanotube Detectors and Spectrometers for the Terahertz Range 

Crystals 2020, 10, 601

DOI:10.3390/cryst10070601

¹Department of Electrical, Computer, and Systems Engineering, RPI  Troy, NY 12180, USA
²Department of Electronic Systems, NUST, O.S. Bragstads plass 2a, 7034 Trondheim, N
⁴Electronics of the Future, Inc., Vienna, VA 22181, USA

Abstract: We present the compact unified charge control model (UCCM) for carbon nanotube field-effect  transistors  (CNTFETs)  to  enable the accurate  simulation  of  the  DC  characteristics  and plasmonic terahertz (THz) response  in the  CNTFETs. Accounting for  the ambipolar  nature of the carrier transport (n-type and p-type conductivity at positive and negative gate biases, respectively), we use n-type and p-type CNTFET non-linear equivalent circuits connected in parallel, representing the ambipolar  conduction in the  CNTFETs.  This allows us to present a realistic non-linear  model that is valid across the  entire voltage  range  and is therefore suitable  for  the  CNTFET design. The important  feature  of  the  model  is that  explicit equations for gate  bias,  current,  mobility,  and capacitance with smoothing parameters accurately describe the device operation near the transition from above- to below-threshold regimes, with scalability in device geometry. The DC performance in  the proposed  compact CNTFET  model  is  validated  by  the  comparison between  the  SPICE simulation and the experimental DC characteristics. The simulated THz response resulted from the validated CNTFET model is found to be in good agreement with the analytically calculated response and  also  reveals  the  bias  and  power  dependent  sub-THz  response  and  relatively  wide  dynamic range   for   detection   that   could   be   suitable   for   THz   detectors.   The   operation   of   CNTFET spectrometers  in the THz  frequency  range  is  further  demonstrated  using  the  present  model.  The simulation exhibits that the CNT-based spectrometers can cover a broad THz frequency band from 0.1 to 3.08 THz. The model that has been incorporated into the circuit simulators enables the accurate assessment  of  DC  performance  and  THz  operation.  Therefore,  it  can  be  used  for the design  and performance estimation of the CNTFETs and their integrated circuits operating in the THz regime.  

Fig: Schematic illustration of the simulation circuit for the CNTFET THz detection

with the open boundary condition at the drain.

Funding: This  work  at  RPI  was  supported  by  the  U.S.  Army  Research  Laboratory  under  the  Cooperative Research Agreement (Project Monitor Dr. Meredith Reed) and by the US ONR (Project Monitor Dr. Paul Maki). 

[paper] An ambipolar homojunction with options

Yanqing Wu

An ambipolar homojunction with options

Nat Electron (2020)

Published 13 July 2020

DOI: 10.1038/s41928-020-0447-3

Circuits capable of reconfigurable logic and neuromorphic functions can be created by exploiting the electronic tunability of two-dimensional tungsten diselenide homojunctions.

Fig: Reconfigurable ambipolar WSe2 homojunction devices and circuits. a, Schematic of a WSe2 homojunction device that consists of two polarity-control embedded gates. b, Using two of these devices, a reconfigurable circuit cell can be created (top) that has a multifunctionality controlled through combinations of gate voltage and drain voltage. The circuit has three input terminals, two of which connect to the polarity gate of one of the devices and the drain of the other device. Using different combinations of the three inputs, seven different Boolean functions can be achieved, including pass, inverter, two-input OR, AND, and borrow-out, as listed in the truth table (bottom). Vds, drain–source voltage; VgA and VgB, gate bias for partial gates A and B, respectively; Vin1, Vin2 and Vin3, input voltages for input terminals 1, 2 and 3, respectively; M1 and M2, homojunction devices 1 and 2, respectively; Vout, output voltage; A, B and C represent logic states of either ‘0’ or ‘1’.

[paper] compact nanowire JAM-MOSFET model

Kamalaksha Baral, Prince Kr Singh, Sanjay Kumar, Manas Ranjan Tripathy,

Ashish Kr Singh, Sweta Chander and S JitA

2-D compact DC model for engineered nanowire JAM-MOSFETs 

valid for all operating regimes

Semiconductor Science and Technology, Vol. 35, No. 8

Abstract: This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate (CG) nanowire junctionless accumulation mode (JAM) MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage (GIDL) has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device. 

Fig: A 2-D cross-sectional view of cylindrical gate nanowire
junctionless accumulation mode MOSFET 

[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC,Grenoble, Sept.14, 2020

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK Workshop as ESSDERC/ESSCIRC Virtual Educational Event

Grenoble, September 14, 2020

Together with local ESSDERC/ESSCIRC Organization Team as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 18th MOS-AK Workshop as ESSDERC/ESSCIRC Virtual Educational Event

Scheduled, subsequent 18th MOS-AK Workshop organized as an integral part of the ESSDERC/ESSCIRC Confernces, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA FOSS and commercial tool developers and vendors. 

MOS-AK Workshop Program

includes 8 webinars by the internationally recognized compact modeling experts: 

W_1 Qucs-S and QucsStudio for compact device modelling.

Mike Brinson

London Metropolitan University (UK)

W_2 Memory Modeling for Neuromorphic Computing

Mansun Chan

Hong Kong University of Science & Technology (HK)

W_3 Compact Modeling of Oxide and Organic Thin Film Transistors

Benjamin Iniguez

Universitat Rovira i Virgili, Tarragona (SP)

W_4 Latest developments of L-UTSOI: 

A compact model dedicated to low-power analog and digital applications in FDSOI technologies

Sébastien Martinie

CEA-Leti, Grenobel (F)

W_5 Overview of the ASM-HEMT Model

Yogesh Chauhan

IIT Kanpur (IN)

W_6 ngspice - current status and developments

Holger Vogt

Fraunhofer IMS, Duisburg (D)

W_7 LDMOS compact modeling and the PSPHV model

Kejun Xia

NXP (USA)

W_8 Nanowire Junctionless ISFETs

Ashkhen Yesayan

Institute of Radiophysics and Electronics National Academy of Sciences (AM)

The MOS-AK program is available online: <http://www.mos-ak.org/grenoble_2020/>

Venue:

Virtual Educational Event at ESSDERC/ESSCIRC  

 

Online Registration 

(any related enquiries can be sent to registration@mos-ak.org)

W.Grabinski on the behalf of International MOS-AK Committee

WG07072020

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[paper] TCAD modeling of neuromorphic systems based on ferroelectric tunnel junctions

Yu He, Wei-Choon Ng and Lee Smith

TCAD modeling of neuromorphic systems based on ferroelectric tunnel junctions

J Comput Electron (2020)

DOI: 10.1007/s10825-020-01544-z

Abstract: A new compact model for HfO2-based ferroelectric tunnel junction (FTJ) memristors is constructed based on detailed physical modeling using calibrated TCAD simulations. A multi-domain configuration of the ferroelectric material is demonstrated to produce quasi-continuous conductance of the FTJ. This behavior is demonstrated to enable a robust spike-timing-dependent plasticity-type learning capability, making FTJs suitable for use as synaptic memristors in a spiking neural network. Using both TCAD–SPICE mixed-mode and pure SPICE compact model approaches, we apply the newly developed model to a crossbar array configuration in a handwritten digit recognition neuromorphic system and demonstrate an 80% successful recognition rate. The applied methodology demonstrates the use of TCAD to help develop and calibrate SPICE models in the study of neuromorphic systems.

Fig: Electric field–polarization relationship. Solid line: multi-domain simulation; dashed line: single-domain simulation; dot: measurement 

[paper] Real-Time Monitoring of Cell Cultures with Nickel Comb Capacitors

Kociubiński, Andrzej, Dawid Zarzeczny, Maciej Szypulski, Aleksandra Wilczyńska, Dominika Pigoń, Teresa Małecka-Massalska, and Monika Prendecka

Real-Time Monitoring of Cell Cultures with Nickel Comb Capacitors

Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska 

10, no. 2 (2020): 32-35

DOI: 10.35784/iapgos.1564

Abstract: The  aim  of  the  study  was  to  present  a  method  for  assessing  the condition of  cell  culture  by  measuring  the  impedance  of  cells  cultured  in  the presence of nickel. For this purpose, an impedance measurement technique using nickel comb capacitors was used. The capacitor electrodes were made using a thin film magnetron sputtering. In the experimental part, the culture of cells of mouse fibroblasts on the prepared substrate was performed. The cell culture lasted 43 hours and showed that the presented technique allows it to be used to analyze the effect of nickel on cells.

Fig: The final nickel electrode array with 8 wells

IEEE Events Reveal #Future #Memory And #Storage https://t.co/lfOq1d8BG3 #paper https://t.co/q7p7pc4ZPd

IEEE Events Reveal #Future #Memory And #Storage https://t.co/lfOq1d8BG3#paper pic.twitter.com/q7p7pc4ZPd

— Wladek Grabinski (@wladek60) July 6, 2020

from Twitter https://twitter.com/wladek60

July 06, 2020 at 11:55AM
via IFTTT

With #128 #Core #Chip, Ampere Seeks to Deliver Reliable Advances [@EETimes] https://t.co/zq3ovp6WPN #paper https://t.co/CLY45rUvGP

With #128 #Core #Chip, Ampere Seeks to Deliver Reliable Advances [@EETimes] https://t.co/zq3ovp6WPN#paper pic.twitter.com/CLY45rUvGP

— Wladek Grabinski (@wladek60) July 6, 2020

from Twitter https://twitter.com/wladek60

July 06, 2020 at 11:45AM
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@ETH integrates #photonics and #electronics on one #chip https://t.co/Lg1KYDF0RS #paper https://t.co/5HKJTzOR51

@ETH integrates #photonics and #electronics on one #chip https://t.co/Lg1KYDF0RS#paper pic.twitter.com/5HKJTzOR51

— Wladek Grabinski (@wladek60) July 6, 2020

from Twitter https://twitter.com/wladek60

July 06, 2020 at 11:42AM
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A Vibrant #Semiconductor #Manufacturing #Model for the #US [Semiwiki] https://t.co/rjT2bSloqX https://t.co/WozbLN0s6h

A Vibrant #Semiconductor #Manufacturing #Model for the #US [Semiwiki] https://t.co/rjT2bSloqX pic.twitter.com/WozbLN0s6h

— Wladek Grabinski (@wladek60) July 6, 2020

from Twitter https://twitter.com/wladek60

July 06, 2020 at 09:30AM
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$1#billion market for #SiC and #GaN https://t.co/D0ukYu8BAK #paper https://t.co/BVZjWuNXlr

$1#billion market for #SiC and #GaN https://t.co/D0ukYu8BAK #paper pic.twitter.com/BVZjWuNXlr

— Wladek Grabinski (@wladek60) July 2, 2020

from Twitter https://twitter.com/wladek60

July 02, 2020 at 03:43PM
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[paper] 1T-1C Dynamic Random Access Memory

1T-1C Dynamic Random Access Memory: 

Status, Challenges, and Prospects 

Alessio Spessot and Hyungrock Oh 

(Invited Paper)

IEEE TED, 67(4), 1382–1393

DOI:10.1109/ted.2020.2963911 

Abstract: This article reviews the status, the challenges, and the perspective of 1T-1C dynamic random access memory (DRAM) chip. The basic principles of the DRAM are presented, introducing the key functional aspects and the structure of modern devices. We present the most relevant historical trends for different modules of the memory chip, such as access device and storage element, reviewing some of the technological challenges faced by industry to guarantee the device shrinking imposed by the economic law. The most recent solutions introduced by the industry in modern DRAM devices for the critical elements are presented. Finally, a survey of the most critical bottleneck for future development is presented, reviewing some of the potential trends and perspectives of DRAM development.

Fig: Review of the historical evolution trend for the cell access device. Various cell access device options are shown. The 4F2 is enabled by the vertical channel. Corresponding technology nodes are included. 

Acknowledgment: The authors would like to thank the imec Core Partners Program for the support. They would also like to thank N. Horiguchi, A. Furnemont, M. H. Na, E. Dentoni Litta, R. Ritzenthaler, and M. Popovici from imec, P. Fazan and C. Mouli from Micron, and C. Kim, Y. Son, and Y. Ji from SK Hynix for the interesting discussions.