[paper] Bulk CMOS Technology at Sub-Kelvin Temperature

Characterization and Modeling of 0.18µm Bulk CMOS Technology 

at Sub-Kelvin Temperature 

Teng-Teng Lu^1,2, Zhen Li^1,2, Chao Luo^1,2, Jun Xu², Weicheng Kong³, 

and Guoping Guo¹ (Member, IEEE) 

IEEE J-EDS, vol. 8, pp. 897-904, 2020

DOI: 10.1109/JEDS.2020.3015265.

¹Key Laboratory of Quantum Information, University of Science and Technology of China, Hefei 230026, China 

²Department of Physics, University of Science and Technology of China, Hefei 230026, China 

³Department of Quantum Hardware, Origin Quantum Computing Company Limited, Hefei 230026, China

Abstract: Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

FIG: IDS-VGS curves of large thin TOX NMOS (a,b,e,f) and PMOS (c,d,g,h) devices at sub-kelvin temperature measured (symbols) and simulated (solid lines). 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2016YFA0301700, in part by the National Natural Science Foundation of China under Grant 11625419, in part by the Anhui initiative in Quantum information Technologies under Grant AHY080000, and in part by the USTC Center for Micro and Nanoscale Research and Fabrication.

[paper] FD-SOI CMOS RF FoM

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

Lucas Nyssens¹ (Graduate Student Member, IEEE), Arka Halder¹, Babak Kazemi Esfeh¹,
Nicolas Planes², Denis Flandre¹ (Senior Member, IEEE), Valeriya Kilchytska¹
and Jean-Pierre Raskin¹ (Fellow, IEEE)
IEEE J-EDS, vol. 8, pp. 646-654, 2020,
DOI: 10.1109/JEDS.2020.3002201

¹UCL, 1348 Louvain-la-Neuve (B) ²ST-Microelectronics, 38920 Crolles (F)

Abstract: This work presents a detailed RF characterization of 28nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (f_T) and maximum oscillation frequency (f_max), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ∼130GHz in f_T and ∼75GHz in f_max is observed for the shortest device (25nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2K and clarifies the origin and limitations of the performance.

FIG: Small-signal equivalent circuit of the RF MOSFETs

Aknowledgement: This work was supported in part by Eniac “Places2Be” and in part by Ecsel “Waytogofast” Projects. The work of Lucas Nyssens was supported by the Fonds de la Recherche Scientifique - FNRS. This paper is based on a paper entitled “28 FDSOI RF Figures of Merit Down to 4.2 K,” presented at the 2019 IEEE S3S Conference.