[paper] BSIM4 CryoModel-4K

Mohammed Saleh Alshaikh

CryoModel-4K: physics-based BSIM4 extension for28 nm bulk CMOS compact modeling at 4K

Nature Scientific Reports (Article in Press) DOI: 10.1038/s41598-026-69962-w

* Device Simulation Laboratory, Department of Electrical Engineering, College of Engineering and Architecture, Umm Al-Qura University, Makkah (SA)

Abstract: Accurate compact transistor models for 28nm bulk CMOS at cryogenic temperatures are essential for reli-able quantum computing interface circuit design. Existing room-temperature BSIM4 models fail to capture carrier mobility freeze-out, subthreshold swing saturation, current kink effects, and threshold voltage shifts at 4K. These failures produce post-fabrication performance deviations exceeding 300% in cryo-CMOS circuits designed using room-temperature models. This paper presents CryoModel-4K, a physics-based compact model that extends BSIM4 to accurately capture 28nm bulk CMOS behavior from 300 to 4K through three integrated correction modules. The Phonon Freeze-Out Mobility Enhancement Module (PFMEM) models the 3 to 8× car-rier mobility enhancement at liquid helium temperatures through a Matthiessen’s-rule combination of phonon, impurity, and surface roughness scattering. It is validated against published 4 K Hall effect measurements. The Cryogenic Subthreshold Swing Saturation Model (CSSM) replaces the classical kT/q thermal voltage with aband-tail tunneling-corrected expression. It accurately reproduces the observed 15 to 25 mV/dec subthreshold swing plateau below 30K. The Impurity Band Transport Kink Model (IBTK) captures the characteristic drain current kink arising from impact ionization triggered floating body effects in the partially frozen bulk substrate. Validation against published wafer-level characterization data for TSMC 28 nm bulk CMOS spanning 300 to 4K across 380 devices on three wafer splits demonstrates less than 5% RMS prediction error for all DC char-acteristics and less than 8% for RF S-parameters up to 10 GHz. Ring oscillator frequency is predicted within6.2% of measured values at 4K, compared to 312.5% error for standard BSIM4. The total SPICE simulation overhead relative to standard BSIM4 is approximately 25%.

FIG: a) Fig. 5 Complete small-signal equivalent circuit of CryoModel-4K for RF simulation, showing the intrinsic MOSFET withPFMEM-modified transconductance, CSSM-corrected output conductance, IBTK kink current source, temperature-depen-dent gate and substrate resistances, and parasitic interconnect elements. Small-signal equivalent circuit valid for operation from 100 MHz to 10 GHz at temperatures from 300 to 4 K. All substrate network elements are temperature-dependent 

b) Output characteristics (𝐼𝐷𝑉D) of a 28 nm NMOS device at 4 K for multiple 𝑉𝐺 values: measured data (symbols) ,CryoModel-4K with IBTK (solid lines), and BSIM4 without kink correction (dashed lines). Device: NMOS Lg = 28 nm, W =  um at T = 4K. VGS stepped from Vth to Vth + 0.5V in 0.1V increments. VDS swept from 0 V to 1.0 V in 25 mV steps. The IBTK captures the characteristic current kink at 𝑉𝐷≈0.5–0.7V

Acknowledgements: The author extends his sincere gratitude to the Umm Al-Qura University, for the invaluable resources and sup-portive environment that made this research possible.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

[paper] Bulk CMOS Technology at Sub-Kelvin Temperature

Characterization and Modeling of 0.18µm Bulk CMOS Technology 

at Sub-Kelvin Temperature 

Teng-Teng Lu^1,2, Zhen Li^1,2, Chao Luo^1,2, Jun Xu², Weicheng Kong³, 

and Guoping Guo¹ (Member, IEEE) 

IEEE J-EDS, vol. 8, pp. 897-904, 2020

DOI: 10.1109/JEDS.2020.3015265.

¹Key Laboratory of Quantum Information, University of Science and Technology of China, Hefei 230026, China 

²Department of Physics, University of Science and Technology of China, Hefei 230026, China 

³Department of Quantum Hardware, Origin Quantum Computing Company Limited, Hefei 230026, China

Abstract: Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18μm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10μm/10μm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

FIG: IDS-VGS curves of large thin TOX NMOS (a,b,e,f) and PMOS (c,d,g,h) devices at sub-kelvin temperature measured (symbols) and simulated (solid lines). 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2016YFA0301700, in part by the National Natural Science Foundation of China under Grant 11625419, in part by the Anhui initiative in Quantum information Technologies under Grant AHY080000, and in part by the USTC Center for Micro and Nanoscale Research and Fabrication.

[paper] FD-SOI CMOS RF FoM

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

Lucas Nyssens¹ (Graduate Student Member, IEEE), Arka Halder¹, Babak Kazemi Esfeh¹,
Nicolas Planes², Denis Flandre¹ (Senior Member, IEEE), Valeriya Kilchytska¹
and Jean-Pierre Raskin¹ (Fellow, IEEE)
IEEE J-EDS, vol. 8, pp. 646-654, 2020,
DOI: 10.1109/JEDS.2020.3002201

¹UCL, 1348 Louvain-la-Neuve (B) ²ST-Microelectronics, 38920 Crolles (F)

Abstract: This work presents a detailed RF characterization of 28nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (f_T) and maximum oscillation frequency (f_max), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ∼130GHz in f_T and ∼75GHz in f_max is observed for the shortest device (25nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2K and clarifies the origin and limitations of the performance.

FIG: Small-signal equivalent circuit of the RF MOSFETs

Aknowledgement: This work was supported in part by Eniac “Places2Be” and in part by Ecsel “Waytogofast” Projects. The work of Lucas Nyssens was supported by the Fonds de la Recherche Scientifique - FNRS. This paper is based on a paper entitled “28 FDSOI RF Figures of Merit Down to 4.2 K,” presented at the 2019 IEEE S3S Conference.