Showing posts with label CMOS technology. Show all posts
Showing posts with label CMOS technology. Show all posts

Mar 30, 2020

conference paper reached 700 reads

M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion," 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 1-4.

Abstract: Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.