postdoc position in Spain related to semiconductor device modeling

As Professor in the Universitat Rovira i Virgili (Tarragona, Catalonia, , Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, junctionless nanowires, III-V MOSFETs, GaN HEMTs, Tunnel FETs, and also organic and metal oxide TFTs.

The candidate should be a person who holds a PhD as awarded after September 1 2009, or who is committed to defend his Ph D thesis in the coming months (before the start of the contract).

Contracts are expected to start after September 2014.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile.

The work may continue the work we did in the framework of some EU-funded projects, such as COMON (about Multi-Gate MOSFETs, GaN HEMTs, and High Voltage MOSFETs), SQWIRE (junctionless Si nanowires) and FlexNET (organic TFTs) . Our contribution in these projects was the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects.

The postdoc position, which will be a contract, will have a duration of up to 2 years. The net salary will be around 1900 Euro/months.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 24 2014

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona, Catalonia
SPAIN.

Standards For FinFETs

   http://electronicdesign.com/eda/synopsys-rich-goldman-explains-effects-standards-2014s-semiconductor-trends 

Rich Goldman, VP of corporate marketing and strategic alliances at Synopsys, recently predicted the top five trends that are likely to drive the global semiconductor industry in 2014. Standards will help, or hurt, each of these trends.

The ever-changing semiconductor industry has experienced and will continue to experience megatrends like no other industry. Recently, Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys, made his predictions about the top five trends that are likely to drive the global semiconductor industry in 2014. Each of these trends can be helped, or hurt, by the domain of standards.

Standards For FinFETs

Karen: You predict that FinFETs will be one of the top five trends in 2014. FinFETs promise lower power consumption and higher performance. Designing and manufacturing FinFETs involve a slew of challenges. How can standards help overcome some of them?

Rich: EDA tools and models are advancing to handle the unique properties and behaviors of FinFETs. For each step in the design cycle, data is transferred from one tool to another. Enabling interoperability and modeling are obvious roles for standards to play and there are already several standards in use today. For example, the Liberty library modeling standard is used to develop FinFET libraries that feed logic synthesis and other advanced tools. Standards for describing low-power design intent are also important. Because low power consumption is a key feature of FinFETs, designers can benefit from using these during the power planning stage. The Unified Power Format (UPF) (IEEE Std. 1801) is effective in capturing the low-power design intent and directing the EDA tools to implement it. The biggest advancements in standards for FinFETs are in the Interconnect Technology Format (ITF) standardized by the IEEE-ISTO and in the new BSIM-CMG (CMOS Multi-Gate) SPICE model.

Karen: Are these standards sufficient for FinFETs today?

Rich: Standards for advanced semiconductor design, including FinFETs, should always evolve. While the standards may suffice for a given technology or geometry node, design and EDA engineers are constantly inventing more effective ways of overcoming challenges. As these engineers learn new techniques, the standards for interoperability and modeling need to be enhanced. It’s a cyclical situation. The standards enable new designs that can render the standards obsolete unless the standards are updated to include new methods and technology. Thus, standards working groups, comprised of tech-savvy engineers and experts in standards development, are part of the overall success of new technologies such as FinFETs.

[continue reading...]

New i-MOS Release

http://i-mos.org/
A new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201401 is available online. In this release, the i-MOS team launched several new services, as well as improved some modules in previous versions. A list of these new features follows:

• Evaluative support for BSIM3 with newly designed interfaces;
• A collection of model parameter cards for your applications;
• A newly implemented double-gate/FinFET model SDDGM; 
• Parameter searching function for all the device models;
• Integrated text editor for composing netlists in circuit simulations;
• Easier entry for your posting of news and events, etc.

For more details and an updated user manual, please see http://i-mos.org

Other related compact/SPICE modeling events and news are listed at:
http://i-mos.org/imos/resources

[Call for Papers] SISPAD2014

https://sites.google.com/site/sispad2014/

This is a call for papers for the 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD2014), to be held September 9-11, 2014, in Yokohama, Japan. This conference provides an opportunity for the presentation and discussion of the latest advances in modeling and simulation of semiconductor devices, processes, and equipment for integrated circuits.

Abstract submission deadline is March 31, 2014.

Workshops:
Two companion workshops will run concurrently prior to the start of the conference on Monday 8th September 2014:

• Workshop 1: Compact Modeling -Enabling Better Insight of Device Features-
  Organizer: Mitiko Miura-Mattausch (Hiroshima University)
• Workshop 2: Carrier Transport in Nano-MOS Transistors: Theory and Experiments(tentative)
  Organizer: Hideaki Tsuchiya (Kobe University) and Yoshinari Kamakura (Osaka University)

Plenary Speakers:

• Augusto Benvenuti (Micron Technology)
  Current status and future prospects of non-volatile memory modeling
• Massimo V. Fischetti (University of Texas at Dallas)
  Physics of electronic transport in low-dimensionality materials forfuture FETs
• Kimimori Hamada (Toyota Motor Corporation)
  TCAD challenge on development of power semiconductor devices for automotive applications

Invited Speakers:

• Mario Ancona (Naval Research Laboratory)
  Nonlinear thermoelectroelastic simulation of III-N devices
• Asen Asenov (University of Glasgow)
  Progress in the simulation of time dependent statistical variability in nano CMOS transistors
• Jean-Pierre Colinge (Taiwan Semiconductor Manufacturing Company)
  Nanowire transistors: pushing Moore's law to the limit
• Tibor Grasser (Vienna University of Technology)
  Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI
• Kohji Mitsubayashi (Tokyo Medical and Dental University)
  Novel biosensing devices for medical applications
• Christian Sandow (Infineon Technologies)
  Exploring the limits of the safe operation area of power semiconductor devices
• Mark Stettler (Intel Corporation)
  Device and process modeling: 20 years at Intel's other fab

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Int. J. Numer. Model. (2014)

Call for IJNM papers: Noise modeling of high-frequency semiconductor devices 

Noise processes in solid-state active devices often determine their fundamental operational limits. This is especially true in situations where a device operates under tight sensitivity and accuracy constraints, as is the case in satellite communication systems, aerospace instrumentation, and deep-space radio astronomy. Today’s ultra-high frequency transistors that meet these demanding low-noise performance characteristics often leverage progressive device downscaling techniques in conjunction with improved semiconductor alloys. 

To enable the design of next-generation low-noise devices, however, accurate and flexible models that characterize the connection between the physics of microscopic noise processes and measurable macroscopic performance are called for. The objective of this Special Issue is to collect and disseminate recent results addressing the topic of modeling and simulation of the macroscopic noise performance of high- frequency transistors including but not limited to GaAs-based and GaN-based field-effect transistors, Si metal–oxide–semiconductor FETs and FinFETs, InP-based high-electron-mobility transistors, and GaAs and SiGe heterojunction bipolar transistors. It is worth pointing out that because of frequency up-conversion phenomena caused by a device’s nonlinearities, low frequency noise processes may strongly impact microwave and millimeter wave behavior as well. Contributions focusing on low-frequency noise modeling therefore will be considered as well. 

This issue will include both invited and contributed manuscripts.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at 

http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/ homepage/ForAuthors.html. 

Potential contributors may contact the Guest Editors to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM’s manuscript website, with a statement that they are intended for this Special Issue. 

Guest Editors: 
Prof. Alina Caddemi University of Messina, Italy Email:
Prof. Ernesto Limiti University of Rome Tor Vergata, Italy Email:

Manuscript submission deadline: July 31, 2014

Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives

In spite of impressive improvements achieved for organic field-effect transistors (OFETs), there is still a lack of theoretical understanding of their behaviors. Furthermore, it is challenging to develop a universal model that would cover a huge variety of materials and device structures available for state-of-the-art OFETs. Nonetheless, currently there is a strong need for specific OFET compact models when device-to-system integration is an important issue. We briefly describe the most fundamental characters of organic semiconductors and OFETs, which set the bottom line dictating the requirement of an original model different from that of conventional inorganic devices. Along with an introduction to the principles of compact modeling for circuit simulation, a comparative analysis of the reported models is presented with an emphasis on their primary assumptions and applicability aspects. Critical points for advancing OFET compact models are discussed in consideration of the recent understanding of device physics.

[1] Kim, C.-H.; Bonnassieux, Y.; Horowitz, G., "Compact DC Modeling of Organic Field-Effect Transistors: Review and Perspectives," Electron Devices, IEEE Transactions on , vol.61, no.2, pp.278,287, Feb. 2014
doi: 10.1109/TED.2013.2281054
URL

[Final Program] EUROSOI 2014, Tarragona, Catalonia, Spain; January 27-29, 2014

The 10th Workshop of the Thematic Network
on Silicon on Insulator Technology, Devices and Circuits 

(EUROSOI 2014) 

Tarragona, Catalonia, Spain 

January 27-29, 2014 

The EUROSOI Workshop is an international forum to promote interaction and exchangesbetween research groups and industrial partners involved in SOI activities all over the world. Following the lively experience of the previous meetings in Granada (2005), Grenoble (2006), Leuven (2007), Cork (2008), Gšteborg (2009), Grenoble (2010), Granada (2011), Montpellier (2012), Paris (2013), EUROSOI 2014 will be held in Tarragona, Catalonia, Spain, and will include a short course program, oral and poster sessions, outstanding key-note presentations, as well as ample rooms for informal discussions. EUROSOI covers recent progress in SOI technologies and will be of interest to materials and device scientists, as well as to process, circuits and applications oriented engineers.

Monday, January 27, 2014

8:30 REGISTRATION
9:05-9:20 SHORT COURSE OPENING
9:20-11:00 PART 1 - EDS MINI-COLLOQUIUM ON SOI TECHNOLOGY 
9:20-10:10 "Process Challenges for Advanced Ge CMOS Technologies" Cor Claeys (IMEC, Leuven, Belgium)
10:10-11.00 "From Floating-Body Memory to Unified Memory on SOI" Sorin Cristoloveanu (INPG, Grenoble, France)
11:00-11:30 COFFEE BREAK
11:30-12:20 "Fabrication Challenges for sub-10 nm Technology nodes" Michael Ostling (KTH, Stockholm, Sweden)
12:20-13:00 "ESD protection of FD and MuG SOI CMOS Chips" Dimitris Ioannou (George Mason University, Fairfax, VA, USA)
13:00-14:30 LUNCH
14:30-15:50 Part 2 -EUROSOI TUTORIAL 
14:30-15:20 "Advanced SOI MOSFET architectures" Jason Woo (UCLA, CA, USA)
15:20-16:00 "SOI CMOS sensors, transistors and circuits for ultra-low-power and harsh environment applications" Denis Flandre (UCL, Louvain-la-Neuve, Belgium)
16:00-16:30 COFFEE BREAK
16:30-18:00 SOI MOSFET CHARACTERIZATION 
16:30-17:20 "On the threshold voltage and interface coupling in advanced SOI MOSFETs" Tamara Rudenko (ISP, Kyiv, Ukraine)
17:20-18:00 "From SOI MOSFET to Spin MOSFET: a modeling approach" Viktor Sverdlov (Tu-Wien, Austria)
20:30 EUROSOI RECEPTION

Tuesday January 28, 2014 

8:15 REGISTRATION
8:45-9:00 OPENING
9:00-11:00 PLENARY SESSIONS 
9:00-9:40 "Taking the next step on advanced HKMG SOI technologies -from 32 nm PD SOIvolume production to 20/28 FD SOI and beyond" Manfred Horstmann (Globalfoundries, Dresden, Germany) invited talk
9:40-10:20 INVITED TALK 
Heike Riel (IBM Research, Zurich) -invited talk
10:20-11:00 "Beyond Si CMOS: Benefits and Challenges " Rafael Rios (Intel, Portland OR, USA) -invited talk
11:00-11:20 COFFEE BREAK
11:20-13:00 SOI MATERIALS TECHNOLOGY AND CHARACTERIZATION 
11:20-11:40 Process and performance of Copper TSVs Lado Filipovic et al.
11:40-12:00 Increasing mobility and spin lifetime with shear strain in thin silicon films Dmitri Osintsev et al.
12:00-12:20 A Comparative Study of Variability of RTN Power Spectral Densities in Bulk and SOIMOSFETs  Louis Gerrer et al.
12:20-12:40 Low temperature noise spectroscopy of p-channel SOI FinFETs Bogdan Cretu et al.
12:40-13:00 Channel Length Influence on the Low-Frequency Noise of Strained 45o Rotated Triple Gate SOI nFinFETs Marcio Alves Sodre de Souza et al.
13:20-14:10 LUNCH
14:10-15:50 SOI MOSFET TECHNOLOGY 
14:10-14:30 Impact of S/D doping profile into electrical properties in nanoscaled UTB2SOI  devices Carlos Sampdero et al.
14:30-14:50 TCAD investigation on a formal Neuron device in 28nm UTBB FDSOI technology Philippe Galy et al.
14:50-15-10 Dual ground plane for high-voltage MOSFET in UTBB FDSOI Technology Antoine Litty et al.
15:10-15:30 Trigate NanoWire MOSFETs Analog Figures of Merit Kilchytska, Valeriya et al.
15:30-15:50 Electrostatically-doped SL FET optimized to meet all the ITRS power targetsat V_DD=0.4 V Elena Gnani et al.
15:50-16:00 COFFEE BREAK
16:00-17:20 SOI MOSFET CHARACTERIZATION 
16:00-16:20 Enhanced Dynamic Threshold Voltage UTBB SOI nMOSFETs Katia Sasaki et al.
16:20-16:40 Parasitic bipolar effect in advanced FD SOI MOSFETs: experimental evidence andgain extraction Fanyu Liu et al.
16:40-17:00 Impact of Lateral Fin-Width Non-Uniformity of FinFETs Clarissa Prawoto et al.
17:00-17:20 Surface effects on split C-V measurements on SOI wafers Luca Pirro et al.
17:20-17:40 Impact of Self-Heating on UTB MOSFET ParametersS ergej Makovejev at al.
17:40-18:00 POSTER BRIEFING (3 MIN EACH) 
18:00-19:40 POSTER SESSION 
Subthreshold Behavior of the PD SOI NMOS Device Considering BJT and DIBL Effects James Kuo et al.
Investigation of Statistical Effects on Reliability of SOI FinFETs Including Sidewall Crystal Orientation Salvatore Amoroso et al.
Powering the More than Moore Electronics with i-MOSLining Zhang et al.
Analysis of Short-Channel Effect in SOTB-MOSFET for Ultra-Low Power Applications Hidenori Miyamoto et al.
2D Analytical Modeling of the Trap-Assisted-Tunneling Current in Double-GateTunnel-FETs Michael Graef et al.
Improved Compact Current Model for FinFETs Based in a New Geometric Approach Arianne Pereira et al.
Capability of the IDS Analytical Model on Predicting the Diamond Variability by Usingthe F-Test Statistic Evaluation Salvador Gimenez et al.
An appraise of the sources of electrical parameters variation in DGMOS Rodrigo Picos et al.
An analytical model for the inversion charge distribution in GAA MOSFETs with rounded corners Francisco Ruiz et al.
The Negative World-line Holding Bias Effect on the Retention Time in FBRAMs Sara Santos et al.
20:30 GALA DINNER

Wednesday January 29, 2014 

8:30-10:30 SOI MOSFET MODELLING 
8:30-8:50 Comprehensive Low-Field Mobility Modeling in Nano-Scaled SOI Channels Zlatan Stanojevic et al.
8:50-9:10 A comprehensive DC current model to describe FinFET self-heating effects Benito Gonz‡lez et al.
9:10-9:30 Channel-Length Impact on Supercoupling Effect in FD-MOSFETs Carlos Navarro et al.
9:30-9:50 Substrate Effect on Threshold Voltage of long and short channel UTBB SOI nMOSFETs Joao Martino et al.
9:50-10:10 In depth characterization of electron transport in 14nm FD-SOI nMOS devices Minju Shin et al.
10:10-10:30 Role of the gate in ballistic nanowire SOI MOSFET Anurag Mangla et al.
10:30-10:50 COFFEE BREAK
10:50-13:10 CIRCUITS, MEMORIES AND SENSORS 
10:50-11:30 "Future of Multi-gate CMOS Technology" Hiroshi Iwai (University of Tokyo, Japan)
11:30-11:50 Impact of SEU on Bulk and FDSOI CMOS SRAM Walter Enrique Calienes Bartra et al.
11:50-12:10 Mechanical Characterization and Modelling of Lorentz Force Based MEMS Magnetic Field Sensors Petros Gkotsis et al.
12:10-12:30 Performance of Source-Follower Buffers Implemented with Junctionless Nanowire nMOS Transistors Michelly Souza et al.
12:30-12.50 PMOSFET-based Pressure Sensors in FD SOI Technology Benoit Olbrechts et al.
12:50-13:10 Performance of Common-Source current mirrors with asymmetric self-cascode SOInMOSFETs  Rafael Assalti et al.
13:10-14:20 LUNCH
14:20-16:10 BEYOND CMOS: NANOWIRES AND JUNCTIONLESS TRANSISTORS 
14:20-15:00 "2D semiconductor channels for ultimate thickness scaling and other versatile applications" Athanasios Dimoulas (IMS, Demokritos, Athens, Greece)
15:00-15:20 A way to solve Poisson equation en cylindrical coordinates to obtain a compact model for Junctionless Gate All Around MOSFET Franois Lime et al.
15:20-15:40 Explicit analytical charge and capacitance models for Junctionless Surrounding GateTransistors  Oana Moldovan et al.
15:40-16:00 Performance Evaluation of Stacked Gate-All-Around MOSFETs Meng-Hsueh Chiang et al.
16:00-16:20 Modeling of Quantization Effects in Nanoscale DG Junctionless MOSFETs Thomas Holtij et al.
16:20-16:30 COFFEE BREAK
16:30-16:50 BEYOND CMOS (TFETs) 
16:30-16:50 Heterojunction TFET inverters providing better performance than multi-gate CMOS at sub 0.3V Vdd Elena Gnani et al.
16:50-17:10 Transport mechanism influence on Vertical Nanowire-TFET analog performance as a function of temperature Paula Agopian et al.
17:10-17:30 3D Modeling of Direct Band-to-Band Tunneling in Nanowire TFETs. Lidija Filipovic et al.
17:30-17:50 Influence of the gate oxide thickness on the Analog Performance of vertical Nanowire-Tunnel FETs with Ge Source Felipe Neves et al.
17:50-18:10 Influence of a precisely positioned channel dopant on the performance of gate-allaround Si nanowire transistor: a full 3D NEGF simulation study Vihar Georgiev et al.
18:10-18:20 CONCLUSIONS AND ANNOUNCEMENTS