#Switzerland has become the 27th European country to join the European High Performance Computing Joint Undertaking #EuroHPC https://t.co/iv6GlZiLtW #paper https://t.co/6yfKdAjoQN

#Switzerland has become the 27th European country to join the European High Performance Computing Joint Undertaking #EuroHPC https://t.co/iv6GlZiLtW #paper pic.twitter.com/6yfKdAjoQN

— Wladek Grabinski (@wladek60) March 27, 2019

from Twitter https://twitter.com/wladek60

March 28, 2019 at 12:06AM
via IFTTT

An EU-funded project has fostered in-depth dialogue between #Europe and #Russia on stepping up #scientific #collaboration https://t.co/XoFy3YYbGF #paper https://t.co/1ME2dBFS8W

An EU-funded project has fostered in-depth dialogue between #Europe and #Russia on stepping up #scientific #collaboration https://t.co/XoFy3YYbGF #paper pic.twitter.com/1ME2dBFS8W

— Wladek Grabinski (@wladek60) March 27, 2019

from Twitter https://twitter.com/wladek60

March 27, 2019 at 11:52PM
via IFTTT

Moore's Law Ending? No Problem. how to stop worrying and love the end of Moore's Law https://t.co/taDtZ1uHt2 #paper

Moore's Law Ending? No Problem. how to stop worrying and love the end of Moore's Law https://t.co/taDtZ1uHt2 #paper

— Wladek Grabinski (@wladek60) March 27, 2019

from Twitter https://twitter.com/wladek60

March 27, 2019 at 09:03PM
via IFTTT

28nm #FDSOI #Analog and #RF Figures of Merit at N2 #Cryogenic Temperatures https://t.co/bAjD2Z8OT1 #paper https://t.co/1zfIXBF0vh

28nm #FDSOI #Analog and #RF Figures of Merit at N2 #Cryogenic Temperatures https://t.co/bAjD2Z8OT1 #paper pic.twitter.com/1zfIXBF0vh

— Wladek Grabinski (@wladek60) March 26, 2019

from Twitter https://twitter.com/wladek60

March 26, 2019 at 10:42PM
via IFTTT

#ARM extends IP support to #18nm #FDSOI https://t.co/Nn8ftvcrOP #model https://t.co/u168ghX5C8

#ARM extends IP support to #18nm #FDSOI https://t.co/Nn8ftvcrOP #model pic.twitter.com/u168ghX5C8

— Wladek Grabinski (@wladek60) March 25, 2019

from Twitter https://twitter.com/wladek60

March 25, 2019 at 11:01PM
via IFTTT

#SOI Silicon Valley #Symposium 2019 https://t.co/SoaSfIy83W #paper https://t.co/OM6toA3GTO

#SOI Silicon Valley #Symposium 2019 https://t.co/SoaSfIy83W #paper pic.twitter.com/OM6toA3GTO

— Wladek Grabinski (@wladek60) March 20, 2019

from Twitter https://twitter.com/wladek60

March 21, 2019 at 12:28AM
via IFTTT

The #World Might Be Better Off #Without #College for Everyone https://t.co/9JgJ5e7BPI #paper https://t.co/lQNNUmCmiA

The #World Might Be Better Off #Without #College for Everyone https://t.co/9JgJ5e7BPI #paper pic.twitter.com/lQNNUmCmiA

— Wladek Grabinski (@wladek60) March 20, 2019

from Twitter https://twitter.com/wladek60

March 21, 2019 at 12:14AM
via IFTTT

K.U. Giering et al., "NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling," in IEEE Transactions on Electron Devices, vol. 66, no. 4, pp. 1662-1668, April 2019. doi: 10.1109/TED.2019.2901907 https://t.co/XqBHjwCXXS #paper https://t.co/4oIN7ev19B

K.U. Giering et al., "NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling," in IEEE Transactions on Electron Devices, vol. 66, no. 4, pp. 1662-1668, April 2019.
doi: 10.1109/TED.2019.2901907 https://t.co/XqBHjwCXXS #paper pic.twitter.com/4oIN7ev19B

— Wladek Grabinski (@wladek60) March 19, 2019

from Twitter https://twitter.com/wladek60

March 19, 2019 at 10:44PM
via IFTTT

Microelectronic conferences #Chip in #Sampa 2019 in São Paulo, SP, Brazil between August 26 to 30, 2019 #SBMicro https://t.co/AwxOarqtAl #paper https://t.co/5Af1tL5q3g

Microelectronic conferences #Chip in #Sampa 2019 in São Paulo, SP, Brazil between August 26 to 30, 2019 #SBMicro https://t.co/AwxOarqtAl #paper pic.twitter.com/5Af1tL5q3g

— Wladek Grabinski (@wladek60) March 18, 2019

from Twitter https://twitter.com/wladek60

March 18, 2019 at 08:06PM
via IFTTT

[mos-ak] [2nd Announcement and C4P] 4th Sino MOS-AK Workshop, Chengdu (CN) June 20-22, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

4th Sino MOS-AK Workshop

Chengdu, China June 20-22, 2019

Together with local UESTC organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 4th Sino MOS-AK Workshop which will be organized at University of Electronic Science and Technology of China (电子科技大学) Chengdu, China between June 20-22, 2019 .

The MOS-AK Workshop in Chengdu, China, is dedicated to advanced electronic and photonic devices. MOS-AK Modeling Association has more than 20 years history of enabling compact/SPICE modeling R&D exchange, please refer to MOS-AK website. With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/optics. With this background, the workshop aims to strengthen a network and discussion forum among experts in the field, provide a forum for the presentation and discussion of the leading edge research and development results of Compact Modeling, Characterization and Simulation techniques for advanced devices, circuits and technologies. Modeling and validation technique of all solid-state devices, including, Si, III-V, power, nanoscale electronic structures and other related new devices are within the scope of the conference. The forefront theme of MOS-AK is "Bridge of Process Technology and Integrated Circuits & Systems Design". 

The MOS-AK Workshop will be held between June 21-22, 2019 at University of Electronic Science and Technology of China (UESTC) in Chengdu, China. The main goal is to exchange compact modeling (CM) related know-how and promote modeling technique to support semiconductor industry. In addition to oral presentations, distinguished experts in the modeling field will be invited to deliver keynote speeches on significant trends, advancements and applications in compact/SPICE modeling domain. On June 20, 2019 we also offer 1day training course related to "SiGe HBTs for mm-Wave Systems Applications" held by Dr. Andreas Pawlak and Dr. Wojciech Debski. In addition, a national students design competition based on GaN HEMT on Si process (OMMIC GaN D01GH) will be also announced. Winners, either single person or team will be awarded with free tapeout, bonus & issued certificate supported by Yifeng-UESTC. 

We welcome industrial partners to show their latest equipment, tools and all other related to the compact/SPICE modeling. After workshop, extremely excellent papers will be selected and recommended for publication in the renowned Journal such as Weily's International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (SCI Index) or International Journal of High Speed Electronics and Systems (EI Index).

Venue:

University of Electronic Science and Technology of China

电子科技大学

Chengdu, China

Important Dates:

Call for Papers - Dec. 2018

2nd Announcement - March 2019

Final Workshop Program - May 2019

MOS-AK Workshop: June 20-22, 2019

Paper Submission deadline: May 20, 2019 (Monday) 

Submission address: yyuan@std.uestc.edu.cn

Notification of Acceptance:  June 3, 2019 (Monday)

Submission of final manuscript: June 10, 2019 (Monday)

Online Registration (to be open in Apr.2019 any related enquiries can be sent to Workshop Secretary: Yuan Yao (Mobile:13086679508))

On the behalf of the Organizing Committee:

Yuhang Xu, UESTC 电子科技大学

Wladek Grabinski, MOS-AK  (EU)

International R&D Adviser :

Min Zhang, XMOD

Advisory Committee:

Yue Hao, Xidian University

Jose Pedro, T-MTT Editor

Yogesh Chauhan, T-ED Editor

WG14032019 

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

[mos-ak] [press note] 2nd MOS-AK India Conference at IIT Hyderabad Feb. 25-27, 2019

2019 IEEE International Conference on Modeling of Systems Circuits and Devices

Organised by Joint Chapter of CAS /ED Societies, IEEE Hyderabad Section

2nd MOS-AK India Conference (IEEE Conference #45395)

Venue: IIT Hyderabad February 25-27, 2019

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its consecutive 2nd International IEEE MOS-AK India Conference 2019 between February 25-27, 2019 at the IIT Hyderabad. The 2nd International IEEE MOS-AK India Conference 2019 is the results of join, collaborative effort. The conference organization would not be possible without direct involvements and financial support provided directly by Collage and IIT Hyderabad as well as the MOS-AK distinguished industrial sponsors including: ams semiconductors, Rhode and Schwarz, Keysight, Synergy, Synopsys, Xilinx and SCL. The MOS-AK India Conference has  also drawn attention of the Joint Chapter of the CAS and EDS Societies of the IEEE Hyderabad Section which provided direct technical program cosponsorship. The Indian Electronic Semiconductor Association (IESA) as well as Swissnex India have provide pronounced dissemination support.

Inauguration session of 2nd International IEEE MOS-AK India Conference 2019 has been chaired by Prof. Mohammed Arifuddin Sohel, MJ College Hyderabad, who welcomed all MOS-AK participants and invited prominent guests Surinder Singh, Director, SCL;  Sebasties Hug, CEO and Consul General of Swissnex;  Sumohan Chenapayya, Dean R&D, IIT Hyderabad;  V. Hanuma Sai, Director, ams semiconductors India Pvt. Ltd.;  N. Venkatesh, Chair, IEEE Hyderabad Section;  Wladek Grabinski, MOS AK (EU);  P.A. Govindacharyulu, General Co Chair, MOS AK India 2019  to open  the 2nd MOS-AK/India Conference.

The MOS-AK India Conference program has been organized as three days scientific R&D event covering recent advances into the technology TCAD simulations, compact/SPICE modeling as well as the device level analog/RF and digital IC designs. The internationally renowned academic and industrial speakers and presenters have delivered 4 tutorial lectures [1-4], 7 keynote talks [5-11], 2 plenary talks [12-13] as well as 22 regular research papers. The MOS-AK Association is an open research forum adequately supporting all R&D activities. An open panel discussion was organized to review challenges and opportunities for women in engineering (WIE) [14]. The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. Presented original unpublished works in all the topics related to the compact/SPICE modeling and its Verilog-A standardization will be submitted for further publication. The conference proceedings will be submitted to IEEE Explore. Best MOS-AK/India papers has been selected and awarded: Gold leaf [15], Silver leaf [16] and Bronze leaf [17] certificates, accordingly. Highest ranked paper authors from regular submission will be invited to extend their R&D contribution in the form of a book chapters in a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoter of MOS-AK/India 2019 Conference. These R&D topics have also received attention of local media and press [18-21]. For more information about each of the R&D contributions, go online to 2nd MOS-AK/India Conference

Photo: All the MOS-AK/India Conference participants at IIT Hyderabad

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses arround the globe thru 2019 year, including:

• 4th Sino MOS-AK Workshop, Chengdu (CN) June 2019
• 17th MOS-AK at ESSDERC/ESSCIRC, Krakow (PL), Sept. 2019
• 12th International MOS-AK Workshop, Silicon Valley (US) Dec. 2019
• 3rd MOS-AK India Conference, Hyderabad, Feb. 2020

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

Tutorials:

[1] Dr. Charvaka Duvvury iT2 Technologies (USA) ESD on-chip protection design 

[2] Dr. Wladek Grabinski MOS-AK (EU) Verilog-A Standardization

[3] Weronika Zubrzycka, AGH, (PL) Radiation effect and Radiation hardening in devices 

[4] Prof. Roberto Murphy, INOE (MX) Characterization of Semiconductor Devices in the High Frequency Regime

Keynote Talks: 

[5] Prof. Yogesh Singh Chauhan, IIT Kanpur (IN) Negative Capacitance Transistors - Modeling, Simulation and Processor Performance

[6] Dr. Surinder Singh, Semiconductor Labs, Chandigarh  (IN), Chandigarh Research at SCL

[7] Weronika Zubrazycka, AGH, (PL) Radiation Effects on Circuits for Space and High-Energy Physics Applications - A case study 

[8] Madabusi Govindrajan, GLOBALFOUNDRIES, Bangalore (IN)  Challenges for RF modeling in the connected era 

[9] Dr. Usha Gogineni, Maxim Semiconductors (IN)  Compact Models for Analog and Mixed Signal Design 

[10] Prof. Santanu Mahapatra, IISc, Bangalore (IN)  Atom-to-Circuit modeling technique for emerging nanomaterial based MOSFETs 

[11] Prof. Gilson Wirth, UFRGS (BR) (Webinar) Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability 

Plenary Talks: 

[12] Prof. Jaijeet Roychowdhury, UC, Berkeley, USA Well-Posed Compact Modeling 

[13] Dr. Ehrenfried Seebacher, ams (A) Compact Modeling for Industrial Applications 

Panel Discussion: 

[14] Dr. G. Uma Devi, Director, NRSC, (IN): Challenges and opportunities for Women in Engineering (WIE). 

Best papers awards:

[15] Chithra and Nagendra Krishnapura, "Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design"

[16] Mohit Ganeriwala, Enrique Marin, Francisco Ruiz and Nihar Mohapatra," A Compact Charge and Surface Potential Model for III-V Quadruple-Gate FETs With Square Geometry"

[17] Suprava Dey, Tara Prasanna Dash, Chinmay Kumar Maiti, Jhansirani Jena, Eleena Mohapatra and Sanghamitra Das," Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering"

Headlines: 

[18] "Swiss interest in India's energy and tech fields" Date: Feb. 27,2019 Publication: The Hindu Edition: Hyderabad

[19] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices" India Education diary  Edition: Online: Prof. Sushmee Badhulika 

[19] Indo-Swiss collaboration needed in education" Date: Feb. 27,2019 Publication: The New Indian express, Edition: Hyderabad

[20] "Switzerland looking forward to stronger ties with Telangana" Feb. 27,2019   Publication: Telangana Today, Edition:  Hyderabad

[21] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices " Date: Feb. 27,2019 Publication: Andhra Jyothi Edition: Hyderabad pp:3

WG14032019

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

B. Tiwari et al., "Oxide TFT Rectifiers on Flexible Substrates Operating at NFC Frequency Range," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 329-334, 2019. doi: 10.1109/JEDS.2019.2897642 https://t.co/cizT5Ek6Uy #paper

B. Tiwari et al., "Oxide TFT Rectifiers on Flexible Substrates Operating at NFC Frequency Range," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 329-334, 2019.
doi: 10.1109/JEDS.2019.2897642 https://t.co/cizT5Ek6Uy #paper

— Wladek Grabinski (@wladek60) March 11, 2019

from Twitter https://twitter.com/wladek60

March 11, 2019 at 08:38PM
via IFTTT

EspoTek Labrador: A small, portable, USB-connected electronics lab-on-a-board that includes an oscilloscope, waveform generator, power supply, logic analyzer, and multimeter.” https://t.co/KjhalAi080 #modeling https://t.co/HwU5AkhWZD

EspoTek Labrador: A small, portable, USB-connected electronics lab-on-a-board that includes an oscilloscope, waveform generator, power supply, logic analyzer, and multimeter.” https://t.co/KjhalAi080 #modeling pic.twitter.com/HwU5AkhWZD

— Wladek Grabinski (@wladek60) March 10, 2019

from Twitter https://twitter.com/wladek60

March 10, 2019 at 03:06PM
via IFTTT

#NanoElectronics Roadmap for #Europe: From Nanodevices and Innovative Materials to System Integration, Solid-State Electronics, 2019 https://t.co/BQz3vAjItM https://t.co/BQz3vAjItM https://t.co/miwhM4i69s #paper

#NanoElectronics Roadmap for #Europe: From Nanodevices and Innovative Materials to System Integration, Solid-State Electronics, 2019 https://t.co/BQz3vAjItMhttps://t.co/BQz3vAjItM https://t.co/miwhM4i69s #paper

— Wladek Grabinski (@wladek60) March 7, 2019

from Twitter https://twitter.com/wladek60

March 07, 2019 at 10:15PM
via IFTTT

#PAPER • OPEN ACCESS Gallium Nitride FET Model V V Orlov and G I Zebrev 2019 IOP Conf. Ser.: Mater. Sci. Eng. 475 012007 https://t.co/gV4Ijifd5g

#PAPER • OPEN ACCESS
Gallium Nitride FET Model
V V Orlov and G I Zebrev 2019 IOP Conf. Ser.: Mater. Sci. Eng. 475 012007 https://t.co/gV4Ijifd5g

— Wladek Grabinski (@wladek60) March 7, 2019

from Twitter https://twitter.com/wladek60

March 07, 2019 at 09:38PM
via IFTTT

S. Amer, M. S. Hasan, M. M. Adnan and G. S. Rose, "#SPICE #Modeling of Insulator Metal Transition: Model of the Critical Temperature," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 18-25, 2019. doi: 10.1109/JEDS.2018.2875627 https://t.co/it8osJWSPM https://t.co/vvGAsWCeYY

S. Amer, M. S. Hasan, M. M. Adnan and G. S. Rose, "#SPICE #Modeling of Insulator Metal Transition: Model of the Critical Temperature," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 18-25, 2019.
doi: 10.1109/JEDS.2018.2875627 https://t.co/it8osJWSPM pic.twitter.com/vvGAsWCeYY

— Wladek Grabinski (@wladek60) March 6, 2019

from Twitter https://twitter.com/wladek60

March 06, 2019 at 07:30PM
via IFTTT

Special MDPI Issue Field-Effect Transistors for Chemical Sensors https://t.co/0w9pQgMqlo #paper https://t.co/nd5EUX1KeD

Special MDPI Issue Field-Effect Transistors for Chemical Sensors https://t.co/0w9pQgMqlo #paper pic.twitter.com/nd5EUX1KeD

— Wladek Grabinski (@wladek60) March 6, 2019

from Twitter https://twitter.com/wladek60

March 06, 2019 at 08:01PM
via IFTTT

#EMM to offer its ultra low power 180nm #CMOS for #MPW service https://t.co/beBG061h9y #model https://t.co/6MOVGvrX97

#EMM to offer its ultra low power 180nm #CMOS for #MPW service https://t.co/beBG061h9y #model pic.twitter.com/6MOVGvrX97

— Wladek Grabinski (@wladek60) March 4, 2019

from Twitter https://twitter.com/wladek60

March 04, 2019 at 10:26PM
via IFTTT

F. Jazaeri and J. Sallese, "Charge-Based EPFL HEMT #Model," in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1218-1229, March 2019. https://t.co/rFwjVUuRbM

F. Jazaeri and J. Sallese, "Charge-Based EPFL HEMT #Model," in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1218-1229, March 2019. https://t.co/rFwjVUuRbM

— Wladek Grabinski (@wladek60) March 1, 2019

from Twitter https://twitter.com/wladek60

March 01, 2019 at 02:15PM
via IFTTT

IIT Kanpur: open compact modeling position

Indian Institute of Technology, Kanpur

The Office of Research & Development

Date: 15-02-2019

Indian Institute of Technology, Kanpur an Institute of national importance, has been in the forefront of engineering & technology education and research & development. The Institute derives strength from its philosophy, vision and values that has led to achievement of academic excellence and promotion of high order technological research. The Institute's R&D Division is looking for suitable Indian nationals including Persons of Indian Origins (PIOs) and Overseas Citizens of India (OCIs) for appointment on the following positions for short-term R&D Projects on contractual basis for a period of maximum five years.

Please forward this job opening with following requirements to your friends/colleagues.

http://iitk.ac.in/new/RnD_Recruitment/

• Hands-on experience of I-V (DC and Pulsed), CV, RF (CW and Pulsed)
• Expertise in Semiconductor Device Modeling and Simulation softwares
• PDK Development & Layout design
• Knowledge of Verilog-A language, PEL/ Python script.
• Strong background in semiconductor device physics
• Good writing skills
• Good Project Management skills

#FOSDEM 2019 – Space and Meaning https://t.co/mQqeuvwtrN #paper

#FOSDEM 2019 – Space and Meaning https://t.co/mQqeuvwtrN #paper

— Wladek Grabinski (@wladek60) February 17, 2019

from Twitter https://twitter.com/wladek60

February 17, 2019 at 10:45PM
via IFTTT

[mos-ak] 2019 IEEE International Conference on Modeling of Systems Circuits and Devices

2019 IEEE International Conference on Modeling of Systems Circuits and Devices

(MOS-AK/India 2019)

Organized by Joint Chapters of CAS / EDS Societies

IEEE Hyderabad Section

Together with the lead sponsors and the conference organization committee we have pleasure to invite to consecutive, 2nd MOS-AK/India Compact Modeling Conference to be hosted at the IIT Hyderabad

Announced, subsequent 2nd MOS-AK/India Conference organized at the IIT Hyderabad, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <http://www.mos-ak.org/india_2019/>

Dates:

MOS-AK/India Conference - February 25-27, 2019

Feb. 25      - ONE day SPICE/Verilog-A Modeling Tutorials

Feb. 26-27 - TWO days SPICE/Verilog-A Modeling Conference

Venue:

Indian Institute of Technology (IIT)

Hyderabad, Kandi

Telangana State, India

Online registration (any related enquiries can be sent secretary.mosak.india@gmail.com or call 9652158557) 

W.Grabinski on the behalf of International MOS-AK Committee

WG02092019

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

IEEE EDS MQ at Hotel Plaza, Begumpet (IN)

Joint Chapter of Electron Devices and Circuits and Systems Societies (ED/CAS)

presents

IEEE Electron Devices Mini Colloquia

Date:  Sunday, 24 February 2019 Time:  3.00 P.M to 6.00 P.M

Venue: Hotel Plaza, Begumpet. Free Registration Link 

For any further details please contact the MQ Coordinators:

• Dr. Mohammed Arifuddin Sohel, Chair, IEEE CAS/EDS joint Chapter
• Dr. A.G. Krishna Kanth, Vice Chair, IEEE CAS/EDS joint Chapter

Registrations: 3:00PM to 3.15 PM

DL Talk 1: 3.15 PM to 4.00PM, Speaker: Prof. Charvaka Duvvury, iT2 Technologies (USA)
Topic: ESD Issues and Challenges for Advanced Semiconductor Technologies

Electro-static Discharge (ESD) has been a constant reliability concern for IC technologies for several decades and it is heading to be a roadblock to newer applications for electronic devices. The seminar will begin with a summary of the understanding about ESD and how this is applied to develop protection at the IC level for Digital, Analog, and RF circuits. This will be followed by a review of the problems posed by advanced technologies beyond the 32 nm node and the corresponding challenge of hitting the available ESD design window while meeting the IO high-speed performance requirements. The talk will conclude with a survey of the upcoming challenges from emerging technologies such as GaN and CNT, as well as IoT applications. 

Speaker Bio: Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI.  He received his PhD in engineering science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta. His experience at Texas Instruments spanned for 35 years in semiconductor device physics with pioneering development work in ESD design. He has also mentored PhD students at several leading US universities on their investigations in ESD research and received Outstanding Industry Mentor Award twice from the SRC. Charvaka has published over 150 papers in technical journals and conferences and holds more than US 75 patents. He co-authored and contributed to 5 books on the subject. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine and machine learning for rapid ESD data analysis. Charvaka is also Fellow of the IEEE.

Hi Tea and Networking: 4.00 PM to 4.15 PM

DL Talk 2: 4.15 PM to 5.00PM Speaker: Dr. Wladek Grabinski, MOS-AK (Switzerland)

Topic: FOSS TCAD/EDA Process/Device Simulations for Compact/SPICE Modeling

Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce.

Speaker Bio: Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. Wladek is the chair of the ESSDERC Track4: "Device and circuit compact modeling" as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ/ Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

DL Talk 3: 5.00PM to 5.45 PM Speaker: Prof. Roberto Murphy, INAOE (Mexico)
Topic: Fundamental Aspects of CMOS RF Modeling and Characterization

As CMOS technology evolves, higher frequencies can be attained while more complex functions and operations become possible in Integrated Circuits. At the design stage, there are several fundamental aspects which have to be taken into account in order to have successful fabrication results, the closest to simulation predictions as possible. Furthermore, this evolution leads to more time-consuming characterization routines, which require both personnel and time to be performed. Some of the aspects dealt with in this talk refer to characterization techniques, substrate network effects, and geometry effects.

Speaker Profile:  Roberto S. Murphy-Arteaga (M´92, SM´02) received his B.Sc. degree in Physics from St. John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from the National Institute for Research on Astrophysics, Optics and Electronics (INAOE), in Tonantzintla, Puebla, México.  He has been a researcher at INAOE since 1988. Since then, he has presented over 110 talks at scientific conferences, directed nine Ph.D. theses, 16 M.Sc. and 2 B.Sc. theses, published more than 140 articles in scientific journals, conference proceedings and newspapers, and is the author of a text book on Electromagnetic Theory.  He is currently a senior researcher with the Microelectronics Laboratory.  Dr. Murphy’s research interests are the physics, modeling and characterization of the MOS Transistor and passive components for high frequency applications, especially for CMOS wireless circuits, and antenna design.  For the last 30 years, he has been active in the organization of conferences, mostly in Latin America, such as the IEEE International Caribbean Conference on Devices, Circuits and Systems; the Latin American Symposium on Circuits and Systems; VLSI-SoC, and others related to microelectronics and IC design. He is a Senior Member of IEEE, a Distinguished Lecturer of the Electron Devices Society, the President of ISTEC, a member of the Mexican Academy of Sciences, and a member of the Mexican National System of Researchers (SNI).

If #Software Is Funded from a #Public Source, Its Code Should Be #OpenSource https://t.co/ZFzJE3SfGK https://t.co/Hq4oF9yqgp

If #Software Is Funded from a #Public Source, Its Code Should Be #OpenSource https://t.co/ZFzJE3SfGK pic.twitter.com/Hq4oF9yqgp

— Wladek Grabinski (@wladek60) February 5, 2019

from Twitter https://twitter.com/wladek60

February 05, 2019 at 08:56PM
via IFTTT

#MIXDES: #Paper submission deadline reminder (4 weeks left) https://t.co/Iw6yG0q157 This year the 26th MIXDES will take place between June 27-29, 2019 in Rzeszów (PL) https://t.co/ewrq66xLoK

#MIXDES: #Paper submission deadline reminder (4 weeks left)https://t.co/Iw6yG0q157
This year the 26th MIXDES will take place between June 27-29, 2019 in Rzeszów (PL) pic.twitter.com/ewrq66xLoK

— Wladek Grabinski (@wladek60) February 4, 2019

from Twitter https://twitter.com/wladek60

February 04, 2019 at 02:55PM
via IFTTT

GnuCap and ngspice at 2019 FOSDEM DevRoom CAD and Open Hardware

Today at #FOSDEM: Felix Salfelder presenting "#Gnucap -- The GNU circuit analysis package Architecture, Algorithms and Applications" addressing Compact Model license considerations
"https://buff.ly/2CeG4DV"


Holger Vogt presenting "#ngspice, current status and future developments" pointing to an obstacle in FOSS CAD/EDA adoption: The newer and more complex Libs/PDKs often come along with encrypted model files.
"https://buff.ly/2DR0Fz6"

RT @devsim: New DEVSIM TCAD Simulator Release https://t.co/q4fiJ9IMWK #tcad #devsim #opensource https://t.co/T4CLcTTQTO

RT @devsim: New DEVSIM TCAD Simulator Releasehttps://t.co/q4fiJ9IMWK #tcad #devsim #opensource https://t.co/T4CLcTTQTO

— Wladek Grabinski (@wladek60) February 1, 2019

from Twitter https://twitter.com/wladek60

February 01, 2019 at 09:00AM
via IFTTT

#IJNM #paper Ye Yuan Zheng Zhong Yong‐xin Guo Shanxiang Mu A novel large‐signal FET model considering trapping‐induced dispersions https://t.co/UYndQ8cKK1” https://t.co/vu0WQtnRgr https://t.co/BiU9XDDiZc

#IJNM #paper Ye Yuan Zheng Zhong Yong‐xin Guo Shanxiang Mu A novel large‐signal FET model considering trapping‐induced dispersions https://t.co/UYndQ8cKK1” https://t.co/vu0WQtnRgr pic.twitter.com/BiU9XDDiZc

— Wladek Grabinski (@wladek60) January 31, 2019

from Twitter https://twitter.com/wladek60

January 31, 2019 at 04:30PM
via IFTTT

Multiphysics Simulation of Biosensors

M. Madec, L. Hébrard, J. Kammerer, A. Bonament, E. Rosati and C. Lallement

Multiphysics Simulation of Biosensors Involving 3D Biological Reaction-Diffusion Phenomena in a Standard Circuit EDA Environmen

IEEE Transactions on Circuits and Systems I: Regular Papers.

doi: 10.1109/TCSI.2018.2885223

Abstract: The topic of this paper is the development of biological models for 3D reaction-diffusion phenomena that can be used in any circuit electronic design automation environment for the simulation of biosensors. Biological systems that involve such 3D phenomena are described by partial differential equations. Our approach consists in discretizing these equations according to the finite-difference method and converting the resulting ordinary differential equations into an assembly of elementary electronic equivalent circuits that are directly simulated with SPICE. The main interest of this approach is the ability to couple such models with third-party SPICE models of electronic circuits, sensors, and transducers, i.e., models from any physical domain ruled by Kirchhoff laws, allowing modeling and simulation of any multi-physics systems in a conventional circuit design environment, here CADENCE. The tool is validated on simple problems for which analytical solutions are known. Then, the interest of the approach is illustrated on the study of a biosensor.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8602461&isnumber=4358591

E.A. Vittoz “CRYSTAL (and MEMS) OSCILLATORS" (course) November 2018 DOI: 10.13140/RG.2.2.25856.07689 https://t.co/NBz9JnZNSL #paper https://t.co/3A1AvRYHd9

E.A. Vittoz “CRYSTAL (and MEMS) OSCILLATORS" (course)
November 2018
DOI: 10.13140/RG.2.2.25856.07689https://t.co/NBz9JnZNSL#paper pic.twitter.com/3A1AvRYHd9

— Wladek Grabinski (@wladek60) January 23, 2019

from Twitter https://twitter.com/wladek60

January 23, 2019 at 10:16AM
via IFTTT

#C4P for a Special Issue of IEEE #TED on Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices https://t.co/0Tcarn2xGC #paper

#C4P for a Special Issue of IEEE #TED on Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices https://t.co/0Tcarn2xGC #paper

— Wladek Grabinski (@wladek60) January 21, 2019

from Twitter https://twitter.com/wladek60

January 21, 2019 at 05:58PM
via IFTTT

A #SPICE Compatible Compact #Model for #Hot-Carrier Degradation in MOSFETs Under Different Experimental Conditions - IEEE Journals & Magazine https://t.co/W7w1zqzXnn

A #SPICE Compatible Compact #Model for #Hot-Carrier Degradation in MOSFETs Under Different Experimental Conditions - IEEE Journals & Magazine https://t.co/W7w1zqzXnn

— Wladek Grabinski (@wladek60) January 19, 2019

from Twitter https://twitter.com/wladek60

January 19, 2019 at 06:15PM
via IFTTT

#roadmap for wider #access to #scientific #results https://t.co/oeNFCdGouJ #opensource https://t.co/DmlOpnUi25

#roadmap for wider #access to #scientific #results https://t.co/oeNFCdGouJ #opensource pic.twitter.com/DmlOpnUi25

— Wladek Grabinski (@wladek60) January 17, 2019

from Twitter https://twitter.com/wladek60

January 17, 2019 at 12:24PM
via IFTTT

#Baidu Announces #OpenSource Edge Computing Platform #OpenEdge https://t.co/PvmANhazM4 https://t.co/7xlZzlMANX

#Baidu Announces #OpenSource Edge Computing Platform #OpenEdge https://t.co/PvmANhazM4 pic.twitter.com/7xlZzlMANX

— Wladek Grabinski (@wladek60) January 16, 2019

from Twitter https://twitter.com/wladek60

January 16, 2019 at 01:58PM
via IFTTT

Environment for #Modeling and #Simulation of #Biosystems, Biosensors, and Lab-on-Chips #LoC - IEEE Journals & Magazine https://t.co/GJpZySIRda

Environment for #Modeling and #Simulation of #Biosystems, Biosensors, and Lab-on-Chips #LoC - IEEE Journals & Magazine https://t.co/GJpZySIRda

— Wladek Grabinski (@wladek60) January 14, 2019

from Twitter https://twitter.com/wladek60

January 14, 2019 at 04:58PM
via IFTTT

#Cryogenic Characterization of 22-nm #FDSOI CMOS Technology for #Quantum #Computing ICs - IEEE Journals & Magazine https://t.co/gg4mCXztz3 #paper

#Cryogenic Characterization of 22-nm #FDSOI CMOS Technology for #Quantum #Computing ICs - IEEE Journals & Magazine https://t.co/gg4mCXztz3 #paper

— Wladek Grabinski (@wladek60) January 14, 2019

from Twitter https://twitter.com/wladek60

January 14, 2019 at 04:56PM
via IFTTT

What #Opening the #MIPS #Architecture Could Mean https://t.co/z43S9tOMNJ #opensource

What #Opening the #MIPS #Architecture Could Mean https://t.co/z43S9tOMNJ #opensource

— Wladek Grabinski (@wladek60) January 13, 2019

from Twitter https://twitter.com/wladek60

January 13, 2019 at 06:58PM
via IFTTT

Postdoctoral positions in device modeling in Spain

As Professor in the in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain., I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, nanowire FETs ,GaN HEMTs, Tunnel FETs, organic and metal oxide TFTs and hyLEDs.

The candidate should be a person who holds a PhD as awarded after January 1 2014.

Contracts will have a duration of two years are expected to start after June 2019.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. 

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

 

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: January 24 2019

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat

 
Benjamin Iñiguez

 

 

 

How #OpenSource Makes Us Better #Human Beings and Brings Us #Together https://t.co/1fUaAVzIqw https://t.co/VHtYEpgD32

How #OpenSource Makes Us Better #Human Beings and Brings Us #Together https://t.co/1fUaAVzIqw pic.twitter.com/VHtYEpgD32

— Wladek Grabinski (@wladek60) January 11, 2019

from Twitter https://twitter.com/wladek60

January 11, 2019 at 09:44AM
via IFTTT

An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model

Ravi Goel, Chetan Gupta, Yogesh S. Chauhan

EE Department, Indian Institute of Technology Kanpur, Kanpur, India

Published in: 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)

Abstract: Recent enhancement in BSIM-BULK (formerly BSIM6) model is presented in this work. The industry standard models like BSIM4, PSP, BSIM-BULK etc. lack the parameters for tuning of transconductance to channel current ratio (gm/Id). gm/Id is also a critical figure of merit for analog applications. Here, we propose an empirical model to enhance the flexibility of gm/Id tuning behavior. The proposed model provides good fitting for different channel lengths and drain bias.

Paper Sections:
I. Introduction
II. An Empirical Model for gm/Id Tuning
III. Model Implementation
IV. Model Validation with TCAD
V. Conclusion

Source:
DOI: 10.1109/UPCON.2018.8597065

#NEXTS Europe secures Europractice services to European academia and industry until end #2021 https://t.co/HsOfzwOY5z #model https://t.co/hXVWSabx05

#NEXTS Europe secures Europractice services to European academia and industry until end #2021 https://t.co/HsOfzwOY5z #model pic.twitter.com/hXVWSabx05

— Wladek Grabinski (@wladek60) January 9, 2019

from Twitter https://twitter.com/wladek60

January 09, 2019 at 02:57PM
via IFTTT

Compact Transcapacitance Model for Short Channel DG FinFETs

Armenian Journal of Physics, vol. 11, issue 4, pp. 269-272

(Proceedings of the Int. Conference on Microwave and THz Technologies and Wireless Comm.)

Ashkhen Yesayan

Institute of Radiophysics and Electronics

Alikhanian Brothers str. 1, 0203 Ashtarak, Armenia

Received 15 November 2018

Abstract: A compact capacitance model is developed accounting for small-geometry effects in FinFETs. While decreasing the channel length, the transcapacitance model becomes very sensitive to all short channel effects, both in moderate and strong inversion regimes. In addition, for short channel devices, we need to take into account the inter-electrode capacitive coupling in the subthreshold regime, which is not significant for long channel devices. The quantum mechanical effects, which are very significant for thin Fins, are included in the model. The effect of mobility degradation on C-V characteristics is also demonstrated. The model was validated with numerical 3D Atlas simulations and a good accuracy of the model has been demonstrated in all operating regimes.

References:

[1] Tech. rep., International technology roadmap for semiconductor (ITRS). 2009.

[2] J.-M. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A. Roy, C. Enz, A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism, Solid-State Electron, vol. 49 no. 3, pp. 485–489. 2005.

[3] A Yesayan, F Prégaldiny, N Chevillon, C Lallement, JM Sallese, Physics-based compact model for ultra-scaled FinFETs, Solid-State Electronics, vol. 62, no1, pp. 165-173, 2011.

[4] Liang X, Taur Y., A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Dev 2004;51(9):1385–91.

[5] Ward D, Dutton R. ,A charge-oriented model for MOS transistor capacitances. IEEE J Solid-State Circ, 1978;13(5):703–8.

[6] Tang M. Etude et modélisation compacte du transistor FinFET. Ph.D. Thesis, University of Strasbourg; December 2009.

[7] Borli H, Vinkenes K, Fjeldly T., Physics-based capacitance modeling of short-channel double-gate MOSFETs. Phys Status Solidi (c) 2008;5(12):3643–6.

[8] Arora N., MOSFET models for VLSI circuit simulation. New York: Theory and Practice, Springer-Verlag; 1993, ISBN:3-211-82395-6

Source:

http://ajp.asj-oa.am/1004/1/EL_4.pdf

#Julia Co-Creators To Receive 2019 James H. Wilkinson #Prize for #Numerical #Software https://t.co/5oLiWnuDZL #opensource

#Julia Co-Creators To Receive 2019 James H. Wilkinson #Prize for #Numerical #Software https://t.co/5oLiWnuDZL #opensource

— Wladek Grabinski (@wladek60) January 9, 2019

from Twitter https://twitter.com/wladek60

January 09, 2019 at 08:12AM
via IFTTT

IEEE TED SI on Compact Modeling for Circuit Design

Special Issue on Compact Modeling for Circuit Design

Benjamin Iñiguez, Wladek Grabinski, Slobodan Mijalković, Kejun Xia, Andries J. Scholten, Yogesh Singh Chauhan, Ananda S. Roy, Sadayuki Yoshitomi, Kaikai Xu

in IEEE Transactions on Electron Devices, vol. 66, no. 1, Jan. 2019.

doi: 10.1109/TED.2018.2884284

Abstract: This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

A total of 60 regular papers were submitted to this Special Issue, of which 21 were accepted. Besides, the Special Issue includes four invited papers. All papers, including the invited ones, were subjected to thorough peer review. A high number of reviewers have participated in this process. This has resulted in a Special Issue containing very high-quality papers.

The published papers target compact modeling aspects for a wide number of devices: several MOSFET structures, tunnel FETs, HEMTs, nanowire FETs, TMD FETs, TFTs, OLEDs, solar cells, photodiodes, and so on.Besides, different operation regimes and analyses are addressed: dc, RF, HV, ballistic regime, variability, reliability, aging, and so on.

The four invited papers also target different topics. The paper by C. C. McAndrew is focused on the successes and challenges of MOS compact models. S. Dongaonkar et al. address the opportunities and challenges of circuit design methodologies ranging from process corners to statistical circuit design. P. Zampardi et al. discuss the industrial view of III–V device compact modeling for circuit design. Finally, Madec et al. target a quite different and challenging environment for the modeling of biosensors, biosystems, and lab-on-chips.

I would like to thank the work done by the rest of the Editors of this Special Issue and also by all the reviewers who participated in this process. And of course, I want to thank all the authors for their interest in submitting papers to this Special Issue. Thanks to authors, reviewers, and editors, this high-quality Special Issue has been possible.

(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

(stream now) Crowdfunding, #FOSDEM, cases, contributions and self-assembly https://t.co/WuZj64zQ92 #opensource

— Wladek Grabinski (@wladek60) December 30, 2018

from Twitter https://twitter.com/wladek60

December 30, 2018 at 08:03PM
via IFTTT

[mos-ak] [press note] 11th International MOS-AK Workshop, Silicon Valley, December 5, 2018

Modeling of Systems and Parameter Extraction Working Group

11th International MOS-AK Workshop

Silvaco Inc. Headquarters, Silicon Valley, December 5, 2018

Summary

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its 11th MOS-AK Workshop at the Silvaco Inc. headquarters in Santa Clara, Calif. on December 5, 2018. The event was co-located with the 2018 IEEE International Electron Devices (IEDM) and the Q4 Compact Modeling Coalition (CMC) meetings. The workshop receives technical program co-sponsorship from the IEEE Santa Clara Valley-San Francisco Chapter of the Electron Devices Society, Europractice, IJHSES as well as NEEDS of nanoHUB.org.

Bogdan Tudor, Silvaco Inc. and Wladek Grabinski, MOS-AK, welcomed more than 30 international academic researchers and modeling engineers. The nine technical compact modeling presentations covered nanoscale technologies, semiconductor devices modeling and advanced IC design.

The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. For more information about each of the presentations, including full abstracts, go online to MOS-AK Workshop Silicon Valley 2018.

The nine topics presented were the following:

1. Silvaco GaN HEMT Compact Modeling Perspective, Bogdan Tudor, Colin Shaw and Sungwon Kong, Silvaco, Inc.
2. GaN HEMT Devices and Modeling for Operational Electronics at Harsh Environments, Saleh Kargarrazi, XLab, Stanford University
3. Impact of Basal Plane Dislocations and Ruggedness of 10 kV 4H-SiC Transistors, Victor Veliadis, PowerAmerica, North Carolina State University
4. Direct measurement of white noise in MOSFETs, Kenji Ohmori, Device Lab Inc.
5. NEREID Technology Roadmap, Enrico Sangiorgi, NEREID, University of Bologna
6. A Physics-Based Compact Model of RRAM for Emerging Applications, Paolo Pavan, University of Modena and Reggio Emilia
7. From Physics to Power, Performance, and Parasitics, Oskar Baumgartner, Global TCAD Solutions GmbH
8. MOS-AK FOSS Compact Modeling Perspective, Wladek Grabinski, IEEE EDS DL, MOS-AK
9. Compact Model of Single TeraFET Spectrometer, Michael Shur, Rensselaer Polytechnic Institute

There were also presentations of Late News with the following topics:

1. CMC Developer Model Software Licenses, Peter Lee, Micron
2. Xyce Parallel Electronic Simulator (Ver. 6.10), Jason Verley, Sandia National Laboratories
3. Call for Papers for ESSDERC/ESSCIRC 2019 in Krakow, Wladek Grabinski, MOS-AK

Photo: Some of the participants of the 11th MOS-AK Workshop at Silvaco Inc. Headquarters in Silicon Valley.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in India, China, Europe, USA and, for the very first time, in Latin America, throughout the coming year, including:

• FOSDEM CAD/EDA DevRoom Feb. 2-3, 2019, ULB Solbosch
• 1st MOS-AK at LAEDC Feb. 25-28, 2019, Armenia, Columbia
• 2nd MOS-AK India Conference Feb. 25-27, 2019, IIT Hyderabad
• 4th Sino MOS-AK Workshop Jun. 20-23, 2019, UECST Chengdu
• MIXDES Special CM Session June 27-29, 2019, Rzeszow
• ESSDERC/ESSCIRC Sept. 23-26, 2019, AHG Krakow

About Silvaco:
Silvaco, Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world's ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

About Europractice IC Service:
The EUROPRACTICE IC Service brings ASIC design and manufacturing capability within the technical and financial reach of any company that wishes to use ASICs. The EUROPRACTICE IC Service, offered by IMEC and Fraunhofer, offers low-cost ASIC prototyping and ASIC small volume production ramp-up to high volume production through Multi Project Wafer - MPW - and dedicated wafer runs.

About MOS-AK Association:
MOS-AK is an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for compact/SPICE model development, validation/implementation and distribution. For more information please visit mos-ak.org

[C4P] EuroSOI-ULIS April 1-3, 2019, Grenoble (F)

5th Joint International EUROSOI and ULIS Conference

at Minatec, Grenoble (F) 

on April 1-3, 2019

The Conference Committee hopes that you will actively participate by submitting high quality papers and will enjoy the conference. The Conference Technical Digest will be published by IEEE and will be available online through IEEE Xplore. The abstract submission deadline is January 15, 2019.

Invited Speakers:

• Dr. Ionut RADU, SOITEC : "SOI technology: from niche to mainstream applications"
• Dr. Anabela VELOSO, IMEC: "Nanowire for ultra-scaled, high-density logic and memory applications"
• Dr. Marc GAILLARDIN, CEA: "Radiation effects in innovative devices"
• Prof. Ru HUANG, Peking University: "Steep slope devices"

More information are provided in the attached 2nd C4P and on the Conference website

DEVSIM 1.0.0 Release #Opensource, #DEVSIM uses finite volume methods to predict behavior of semiconductor devices. In addition to drift-diffusion equations, the density-gradient method can be used to account for quantum effects near boundaries. https://t.co/q4fiJ9IMWK

DEVSIM 1.0.0 Release #Opensource, #DEVSIM uses finite volume methods to predict behavior of semiconductor devices. In addition to drift-diffusion equations, the density-gradient method can be used to account for quantum effects near boundaries. https://t.co/q4fiJ9IMWK

— Wladek Grabinski (@wladek60) December 20, 2018

from Twitter https://twitter.com/wladek60

December 20, 2018 at 10:49AM
via IFTTT

Compact Transistor Modeling with Radiation Effects

A Radiation-Hardened Instrumentation Amplifier for Sensor Readout Integrated Circuits in Nuclear Fusion Applications

Kyungsoo Jeong 1, Duckhoon Ro 1, Gwanho Lee 2  Myounggon Kang 2* and Hyung-Min Lee 1*

1 School of Electrical Engineering, Korea University, Seoul 02841, Korea; jksoo2002@korea.ac.kr (K.J.); roduckhoon@korea.ac.kr (D.R.)

2 Department of Electronics Engineering, Korea National University of Transportation, Chungju 27469, Korea; ghlee@ut.ac.kr

* Correspondence: mgkang@ut.ac.kr (M.K.); hyungmin@korea.ac.kr (H.-M.L.); Tel.: +82-43-841-5164 (M.K.); +82-2-3290-3219 (H.-M.L.)

Abstract: A nuclear fusion reactor requires a radiation-hardened sensor readout integrated circuit (IC), whose operation should be tolerant against harsh radiation effects up to MGy or higher. This paper proposes radiation-hardening circuit design techniques for an instrumentation amplifier (IA), which is one of the most sensitive circuits in the sensor readout IC. The paper studied design considerations for choosing the IA topology for radiation environments and proposes a radiation-hardened IA structure with total-ionizing-dose (TID) effect monitoring and adaptive reference control functions. The radiation-hardened performance of the proposed IA was verified through model-based circuit simulations by using compact transistor models that reflected the TID effects into complementary metal–oxide–semiconductor (CMOS) parameters. The proposed IA was designed with the 65 nm standard CMOS process and provides adjustable voltage gain between 3 and 15, bandwidth up to 400 kHz, and power consumption of 34.6 µW, while maintaining a stable performance over TID effects up to 1 MGy.

Electronics 2018, 7, 429; doi:10.3390/electronics7120429
Received: 22 November 2018; Accepted: 9 December 2018; Published: 12 December 2018

Why #NASA #opensource the #Rover https://t.co/BtUmzR7hzr

Why #NASA #opensource the #Rover https://t.co/BtUmzR7hzr

— Wladek Grabinski (@wladek60) December 19, 2018

from Twitter https://twitter.com/wladek60

December 19, 2018 at 07:41AM
via IFTTT