[paper] Zener diode compact modeling and simulation

Mike Brinson

Modelling and simulation of Zener diode noise in the time domain

International Journal of Numerical Modelling Electronic Networks Devices and Fields

January 2023

DOI: 10.1002/jnm.3090

1 Centre for Communications Technology, London Metropolitan University, London, UK.

Abstract: This paper presents a new time domain Zener diode compact model for transient noise simulation. SPICE2 and SPICE3 use piece-wise linear time dependent sources for generating complex waveforms. This approach is not practical when applied to randomly generated noise. Today, through on-going improvements to freely available Circuit simulation tools, SPICE noise generation has moved to a new level. Ngspice, for example, computes white Gaussian noise ‘on-the-fly' as transient Simulation progresses. The proposed model has a simple behavioral structure that supports time domain shot, flicker, and thermal noise. The physical properties of the proposed model are introduced in the second section. This is followed by an evaluation of model performance in the third and fourth sections, including static DC, dynamic Charge, and transient noise characterization. Finally, the fifth section summarizes the conclusions of the research.

FIG: QuCS-S/Ngspice Zener diode behavioural model: subcircuit schematic drawing; intermediate equations and limexp function definition.

DATA AVAILABILITY STATEMENT: Data Sharing not applicable to this article as no datasets were generated or analyzed during the current study.

[paper] DMT-core: A Python Toolkit for Semiconductor Device Engineers

Mario Krattenmacher^1,2, Markus Müller^1,2, Pascal Kuthe^1,2, and Michael Schröter^1,2

DMT-core: A Python Toolkit for Semiconductor Device Engineers

Journal of Open Source Software, 7(75), 4298

DOI: 10.21105/joss.04298

1 CEDIC, TU Dresden, Dresden (D)

2 SemiMod GmbH, Dresden (D)

Abstract: Semiconductor device engineers are faced by a number of non-trivial tasks that can be solved efficiently using software. These tasks include, amongst others, data analysis, visualization and processing, as well as interfacing various circuit and Technology-Computer-Aided-Design (TCAD) simulators. In practice, custom ‘home-made’ scripts of varying quality are employed to solve these tasks. It is often found that fundamental software engineering concepts, such as Test-Driven-Development (Shull et al., 2010), or the use of state-of-the-art version control tools (e.g. Git) and practices (e.g. continuous integration, CI), are not utilized by these scripts. The issues inflicted by this practice include:

• The analysis/visualization/generation of data becomes difficult to reproduce.
• Device engineers work far from their maximum work-efficiency, as they are hindered, instead of empowered, by the software infrastructure.
• Knowledge built-up, possibly over decades, may be lost when developers leave a company or institution.

The Device Modeling Toolkit (DMT) presented here aims to solve these issues. DMT provides a Python library that offers:

• classes and methods relevant to commonly used device engineering tasks
• several abstract base classes for implementing new interfaces to various types of simulators
• concrete implementations of the abstract base classes for open-source simulators such as Ngspice (Vogt, 2022), Xyce (Keiter et al., 2014) or Hdev (Müller et al., 2022).

DMT-based simulations allow data generation, workflow implementation and visualization to be implemented in a single file, enabling more efficient cooperation and more reproducible research (Stodden et al., 2016). Basic principles in software engineering, such as unit testing,v ersion control, and documentation, are adhered to so that others can use and contribute to the software.

FIG: DMT interfacing a circuit simulator and corresponding data flow.

Related Publications: DMT is used internally by CEDIC staff in research and by SemiMod for commercial purposes. It has also been used by cooperating institutions and companies. The project has been used inthe following contexts:

• for circuit simulations (Weimer et al., 2022),
• for TCAD simulations and plotting (Markus Muller et al., 2021),
• for circuit and TCAD simulations (M. Muller et al., 2022),
• for model parameter extraction (Müller & Schröter, 2019) and
• for model parameter extraction and TCAD simulation (Phillips et al., 2022).

In addition, DMT has been cited in (Grabinski, 2019; Kuthe et al., 2020; Müller et al., 2019,

2021).

Related Projects: DMT directly uses the VerilogAE (Kuthe et al., 2020) for accessing all information in Verilog-AMS files. The TCAD simulator Hdev (Müller et al., 2022) uses the class DutHdev as its Python interface.

Acknowledgements: This project would not have been possible without our colleagues Dipl.-Ing. Christoph Weimer and Dr.-Ing. Yves Zimmermann. We particularly acknowledge Wladek Grabinski for his efforts to promote the use of open source software in the semiconductor community.

REF:

Shull, F., Melnik, G., Turhan, B., Layman, L., Diep, M., & Erdogmus, H. (2010). What do we know about test-driven development? IEEE Softw., 27(6), 16–19. https://doi.org/10.1109/MS.2010.152
Vogt, H. (2022). Ngspice, the open source Spice circuit simulator - Intro. http://ngspice. sourceforge.net/
Keiter, E. R., Mei, T., Russo, T. V., Schiek, R. L., Sholander, P. E., Thornquist, H. K., Verley, J. C., & Baur, D. G. (2014). Xyce Parallel Electronic Simulator Reference Guide , Version 6 . 2 (September). Sandia National Laboratories (SNL). https://doi.org/10.2172/1826862
Müller, M., Mothes, S., Claus, M., & Schröter, M. (2022). Hdev: A 1D and 2D Hydrodynamic/Drift-Diffusion solver for SiGe and III-V HBTs. J. Open Source Software
Stodden, V., McNutt, M., Bailey, D. H., Deelman, E., Gil, Y., Hanson, B., Heroux, M. A., Ioannidis, J. P. A., & Taufer, M. (2016). Enhancing reproducibility for computational methods. Science, 354(6317), 1240–1241. https://doi.org/10.1126/science.aah6168 
Grabinski, W. (2019). FOSS TCAD/EDA tools for compact modeling. Arbeitskreis Bipolar.
https://www.iee.et.tu-dresden.de/iee/eb/forsch/AK-Bipo/2019/7-MOS-AK-Association_wgr_BipAK19.pdf

[paper] ULTRARAM Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli, 

Richard Beanland and Manus Hayne

ULTRARAM: A Low-Energy, High-Endurance, Compound-Semiconductor Memory 

on Silicon

First published: 05 January 2022

Adv. Electron. Mater. 2022, 8, 2101103

DOI: 10.1002/aelm.202101103

Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10ms duration program/erase pulses of ≈2.5V, a remarkably fast switching speed for 10 and 20µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

FIG: a) Schematic cross-section of ULTRARAM device concept with corresponding material layers. The floating gate (1: FG), triple-barrier resonant-tunneling structure (2: TBRT), and readout channel (3) are highlighted. Arrows indicate the direction of electron flow during program/erase operations; b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.

Mixed Signal SoC design Marathon using eSim & SKY130

Marathon Date : 23 Sept. - 8 Oct. 2022

The following submissions are adjudged as Outstanding, Excellent, Very good and Good by the FOSSEE and the VSD teams.

• Outstanding
• Excellent
• Very Good
• Good

List of Outstanding Circuits:

#	Participant	Circuit	Institute	GitHub
1	Milad Vafaieenezhad	Window Comparator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Shahed University	View Repo
2	Krunal Badlani	Crack Sensing Circuit	Indian Institute of Technology Hyderabad	View Repo
3	Karuppusamy V	Flash Type ADC	Bannari Amman Institute of Technology	View Repo
4	Inderjit Singh Dhanjal	32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology	K. J. Somaiya College of Engineering	View Repo
5	Tanay Das	Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback	Sikkim Manipal Institute of Technology	View Repo
6	Jayanth Nedunuri	Implementation of 4 bit Two Step Flash ADC	Jyothishmathi institute of Technology and Science	View Repo
7	Aishwarya Balkrishna Patil	Design and Implementation of Automatic Security Monitoring System	Kolhapur Institute of Technology’s College of Engineering, Kolhapur	View Repo
8	Swagatika Meher	3-bit CMOS based TIQ comparator Flash ADC	Odisha University of Technology and Research, Bhubaneswar, Odisha	View Repo
9	Surya V	3-bit Flash ADC using ROM-based Encoder	National Institute of Technology, Tiruchirapalli	View Repo
10	Sanket M Mantrashetti	Design of 8x8 SRAM based on 6T SRAM cell	R. V. College of Engineering	View Repo
11	Avishek Choudhary	10-bit C2C DAC	Thapar Institute of Engineering and Technology	View Repo
12	Nalinkumar S	Implementation of Quadruple - Window Comparator Along with Prioritized MOD-16 Counter for Data Line Multiplexing Operation	Madras Institute of Technology Campus, Anna University	View Repo
13	Rubankumar D	Astable Multivibrator Along with MOD-16 Counter for Counting Based Data Line Selection Operation	Madras Institute of Technology Campus, Anna University	View Repo
14	Vanshika Tanwar	Implementation of 3 Bit Flash ADC performed in eSim	Dronacharya Group Of Institutions, Greater Noida	View Repo
15	Ravi Prakash Vishwakarma	8 Bit Counter/Ramp Type ADC	Madan Mohan Malaviya University Of Technology	View Repo
16	E Balakrishna	Implementation of 4 Bit Flash ADC mixed signal circuit using 130nm performed in eSim	Dronacharya Group of Institution, Greater Noida	View Repo

Contact eSim-fossee:
For more information about the marathon, write to us at contact-esim[at]fossee[dot]in

Call for Papers - IEEE Special Issue of T-ED

Call for Papers - IEEE Special Issue of T-ED on #Semi #Device #Modeling for #Circuit and #System Design Submission Deadline: 30 April 2023 Learn More & Submit: https://t.co/GdNbNufQxH #ElectronDevicesSociety #ElectronDevices #semiconductor #emergingsem…https://t.co/iGSHSjXaxn

— Wladek Grabinski (@wladek60) Jan 19, 2023

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