[paper] Efficient Long-Channel MOSFET Model

Ananda Sankar Chakraborty

Efficient Long-Channel MOSFET Model 

with SPICE-enabled Lambert W Function for Universal Application

Silicon (2025): 1-10; DOI 0.1007/s12633-025-03576-1

1 ETCE, Indian Institute of Engineering Science and Technology, Shibpur (IN)

Abstract: A novel, accurate charge-based MOSFET long-channel computational model is presented, which is portable and can be used across the electrical engineering domains ranging from sensing to power electronics, both under sub-threshold as well as super-threshold regime of MOSFET operation. The proposed physics-based model can be universally used to any long-channel MOS-transistor, as it does not depend on any empirical factor and features extremely good computational efficiency. The model uses a novel two-step charge linearization, resulting into accurate drain current and charge model – valid for both the subthreshold and super-threshold regime of long-channel MOSFET operation. Another salient feature of the proposed model is a novel SPICE-compatible numerical solution strategy for the principal branch of the Lambert W function (W0(x) for {x ∈ R | x ≥ 0}). The algorithm is faster than present industry standard implementations, computationally efficient, accurate with maximum percentage error≈10−14% and therefore may be incorporated in a SPICE engine for electrical design and optimization. The proposed computationally efficient long channel MOSFET model is validated against thorough TCAD simulations upto the fourth derivative and has been found to have fast convergence along with much higher degree of accuracy compared to existing MOSFET models.

FIG: Bulk-MOSFET structure: its current (I_DS) and conductance (g_DS) vs Drain Voltage (V_DS)

(Line: proposed model, symbol: TCAD)

[paper] Bioinspired Phototransistor

Ruyue Han, Dayu Jia, Bo Li, Shun Feng, Guoteng Zhang, Yun Sun, Zheng Han, Chi Liu, Hui-Ming Cheng and Dong-Ming Sun

Bioinspired phototransistor with tunable sensitivity for low-contrast target detection

Light Sci Appl 15, 12 (2026) DOI: 10.1038/s41377-025-02051-1

Shenyang National Laboratory for Materials Science, Institute of Metal Research, CAS, Shenyang (CN)
School of Materials Science and Engineering, University of Science and Technology of China, Shenyang (CN)
School of Information Institution, Liaoning University, Shenyang (CN)
State Key Laboratory of Quantum Optics and Quantum Optics Devices, Shanxi University, Taiyuan (CN)
Collaborative Innovation Center of Extreme Optics, Shanxi University, Taiyuan (CN)
Liaoning Academy of Materials, Shenyang (CN)
Faculty of Materials Science and Engineering, Shenzhen Institute of Advanced Technology, CAS, Shenzhen (CN)

Abstract: Accurate recognition of low-contrast targets in complex visual environments is essential for advanced intelligent machine vision systems. Conventional photodetectors often suffer from a weak photoresponse and a linear dependence of photocurrent on light intensity, which restricts their ability to capture low-contrast features and makes them susceptible to noise. Inspired by the adaptive mechanisms of the human visual system, we present a molybdenum disulfide (MoS2) phototransistor with tunable sensitivity, in which the gate stack incorporates a heterostructure diode—composed of O-plasma-treated MoS2 and pristine MoS2—that serves as the photosensitive layer. This configuration enables light-intensity-dependent modulation of the diode’s conductance, which dynamically in turn alters the voltage distribution across the gate dielectric and transistor channel, leading to a significant photoresponse. By modulating the gate voltage, the light response range can be finely tuned, maintaining high sensitivity to low-contrast targets while suppressing noise interference. Compared to conventional photodetectors, the proposed device achieves a 1000-fold improvement in sensitivity for low-contrast signal detection and exhibits significantly enhanced noise immunity. The intelligent machine vision system built on this device demonstrates exceptional performance in detecting low-contrast targets, underscoring its promise for next-generation machine vision applications.

FIG: Performance of tunable-sensitivity phototransistor array. (a) Optical image of a 3 × 3 phototransistor array (scale bar: 200 μm). (b) Magnified image of an individual sensor unit (scale bar: 10 μm). 

(c) IDS−VGS curves of the 9 phototransistors in dark and under 516-nm light at VDS = 0.1 V. 

Acknowledgements: This work was supported by the National Key Research and Development Program of China (2021YFA1200801), the National Natural Science Foundation of China (No. 62304226, 52188101, 62450124, 62125406), the China Postdoctoral Science Foundation (2024T170946, 2023M733574), the Excellent Youth Fund Project of Liaoning Province (2023JH3/10200003), the Outstanding Youth Fund Project of Liaoning Province (2025JH6/101100015), the Special Projects of the Central Government in Guidance of Local Science and Technology Development (2024010859-JH6/1006), the Special Research Assistantship Project of the Chinese Academy of Sciences (E455L502), the China Postdoctoral Science Foundation under Grant Number GZB20230776, the Liaoning Provincial Key Laboratory of Public Opinion and Network Security Information System (d252453002), the Artificial Intelligence Technology Innovation Project of Liaoning Province (Grant No. 2023JH26/10300019), the Young Top-notch Talents of the National High-level Talent Special Support Program, the basic scientific research project of universities funded by the Liaoning Provincial Department of Education (LJ212510140016) and the Liaoning Province High-quality Industry-University Cooperation and Collaborative Education Project (241201160090747). The authors gratefully acknowledge Dr. Bing Yang and Dr. Honglei Chen from the Institute of Metal Research for their valuable support in HRTEM-EDS characterization.

[paper] 60GHz Class-AB PA in 22nm FD-SOI CMOS

Dimitrios Georgakopoulos, Vasileios Manouras and Ioannis Papananos

A 60-GHz Current Combining Class-AB Power Amplifier in 22 nm FD-SOI CMOS

Microwave 2026, 2(1), 2; DOI: 10.3390/microwave2010002

* School of Electrical and Computer Engineering, National Technical University of Athens, (GR)

Abstract: This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ( 𝑃𝑠𝑎𝑡 ) of 20.2 dBm, and a maximum large-signal gain (𝐺𝑚𝑎𝑥 ) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes. 

FIG: Top-level schematic of the overall mm-Wave PA, including layout of all passive networks

[paper] Compact IV Model for DG MoS2 FETs

Ahmed Mounir, Francois Lime, Alexander Kloes, Alexandros Provias, Theresia Knobloch, 

K. P. O’Brien, Tibor Grasser and Benjamin Iniguez

Compact I–V Model for Double-Gated MoS2 FETs Including Short-Channel Effects

IEEE TED, Vol. 72, No. 12, Dec 2025

DOI: 10.1109/TED.2025.3622099

Rovira i Virgili University, Tarragona (SP)
THM University of Applied Sciences, Giessen (D)
Technical University of Vienna (A)
Intel Foundry Technology Research, Hillsboro (US)

Abstract: This article presents a physics-based analytical compact model for double-gated molybdenum disulfide (MoS2) field effect transistors (FETs), incorporating key physical and short-channel effects (SCEs), such as mobility degradation and velocity saturation. The model is developed from a unified charge control model by evaluating the charge density within the 2D MoS2 layer, represented using the Lambert W function, which provides an analytical expression valid and continuous from the subthreshold to the above threshold regime. The drain current is then derived from this unified charge control model, and as a function of closed-form equations for the charge densities at the source and drain ends of the channel. Despite its simplicity, the model shows excellent agreement with experimental data for channel lengths down to 60nm, making it a powerful tool for accurately predicting the performance of downscaled devices. By including SCEs, this work extends previous modeling efforts and provides a more comprehensive framework for the simulation and optimization of 2D material-based FETs in circuit design.

FIG: Cross-sectional view of the double-gated MoS2 FET, showing the top gate oxide stack made of Al2O3 and HfO2, with the local back gate oxide consisting of HfO2. Validation of the compact model against experimental data for double-gate MoS2 FET L = 60nm (bottom line)

Acknowledgements: This work was supported in part by European Union Bayesian inference with flexible electronics for biomedical applications (BAYFLEX) under Contract 101099555 and in part by the Ministry of Science of Spain under Contract PID2021122399OB-I00

[book] CMOS RF and mm-Wave Transceivers and Synthesizers

CMOS RF and mm-Wave Transceivers and Synthesizers

(1st ed. 2025)

By Bharatha Kumar Thangarasu, Nagarajan Mahalingam, 

Kaixue Ma, Kiat Seng Yeo

Jenny Stanford Publishing

DOI 10.1201/9781003673569

Abstract: Power consumption has become a critical concern in RF/mm-wave integrated circuit (IC) design thanks to new applications from 5G, mobile computing, artificial intelligence, and the Internet of Things. However, big challenges lie ahead for chip designers when they choose to develop ICs using silicon technology for low-power and high-data-rate applications. This is because silicon technology suffers from undesirable energy dissipation due to its lossy substrate and high resistive wiring loss at GHz frequencies. Nonetheless, silicon remains the most suitable material, satisfying the demands of a rapidly growing semiconductor market through low fabrication cost and ease of achieving system-on-chip or system-in-package integration. While long being neglected, low-power RF/mm-wave design has vaulted to the forefront of attention in recent years due to the demand for ultra-low-power transceivers to achieve sustainability. Designing genuinely ubiquitous transceivers for these new applications requires innovations in both system architecture and circuit implementation.

This book closes the gap between a typical textbook with theories that are difficult to understand and a design-oriented book that offers little insight into actual theories. It evaluates and discusses different circuit topologies, receiver and transmitter architectures, phase-locked loop performance metrics, phase noise analysis, and sub-system-level designs that have yet to be reported in other books.

Table of Contents

• Chapter 1: CMOS RF Active and Passive Devices (pp. 1–49)
• Chapter 2: Transceiver Building Blocks (pp. 50–126)
• Chapter 3: Receiver Sub-System (pp. 127–193)
• Chapter 4: Transmitter Sub-System (pp. 194–238)
• Chapter 5: Transceiver System Integration (pp. 239–347)
• Chapter 6: CMOS RF/mm-Wave Oscillators (pp. 348–401)
• Chapter 7: CMOS Frequency Synthesizers (pp. 402–482)