[paper] Efficient Long-Channel MOSFET Model

Ananda Sankar Chakraborty

Efficient Long-Channel MOSFET Model 

with SPICE-enabled Lambert W Function for Universal Application

Silicon (2025): 1-10; DOI 0.1007/s12633-025-03576-1

1 ETCE, Indian Institute of Engineering Science and Technology, Shibpur (IN)

Abstract: A novel, accurate charge-based MOSFET long-channel computational model is presented, which is portable and can be used across the electrical engineering domains ranging from sensing to power electronics, both under sub-threshold as well as super-threshold regime of MOSFET operation. The proposed physics-based model can be universally used to any long-channel MOS-transistor, as it does not depend on any empirical factor and features extremely good computational efficiency. The model uses a novel two-step charge linearization, resulting into accurate drain current and charge model – valid for both the subthreshold and super-threshold regime of long-channel MOSFET operation. Another salient feature of the proposed model is a novel SPICE-compatible numerical solution strategy for the principal branch of the Lambert W function (W0(x) for {x ∈ R | x ≥ 0}). The algorithm is faster than present industry standard implementations, computationally efficient, accurate with maximum percentage error≈10−14% and therefore may be incorporated in a SPICE engine for electrical design and optimization. The proposed computationally efficient long channel MOSFET model is validated against thorough TCAD simulations upto the fourth derivative and has been found to have fast convergence along with much higher degree of accuracy compared to existing MOSFET models.

FIG: Bulk-MOSFET structure: its current (I_DS) and conductance (g_DS) vs Drain Voltage (V_DS)

(Line: proposed model, symbol: TCAD)

[paper] Single Gate Extended Source Tunnel FET

Jagritee Talukdar^a, Gopal Rawat^b, Bijit Choudhuri^a, Kunal Singh^c, Kavicharan Mummaneni^a

Device Physics Based Analytical Modeling for Electrical Characteristics of Single Gate Extended Source Tunnel FET (SG-ESTFET)

Superlattices and Microstructures (2020): 106725

DOI: 10.1016/j.spmi.2020.106725

^aDECE, NIT Silchar, Assam, India
^bDECE, NIT Hamirpur, Himachal Pradesh, India
^cDECE, NIT Jamshedpur, Jharkhand, India

Abstract: In this paper, a 2D analytical model for Single Gate Extended Source Tunnel FET has been developed which is based on the solution of Poisson’s equation simplified using parabolic approximation method. Different electrical characteristics of device physics such as surface potential, drain current, lateral, and vertical electric field of SG-ESTFET are studied incorporating various parameters like mole fraction of SiGe layer, gate dielectric constants, etc. Furthermore, in modeling and simulation, the depletion region of the drain side is included considering the effect of the fringing field. The comercial TCAD device simulator has been used to verify the accuracy and validity of the proposed analytical model for various electrical parameters such as gate to source voltage, mole fraction, and gate dielectric constants. The validity of the proposed model is confirmed by observing a decent agreement between modeling and simulation. The proposed compact model delivers quick and accurate values of various performance parameters.

Fig: 2D schematic device structure of SG-ESTFET