CppSim: has been actively used since 2002. It is used for commercial and academic purposes. It performs system-level simulations of mixed-signal circuits. It automatically produces, compiles, and executes C++ code per the schematic design you produce.
Electric: among one the powerful CAD systems which can handle different types of circuit design tasks including MOS, Bipolar, schematics, printed circuitry, hardware description languages, etc. It can analyze design rule checking, simulation, and network comparison. It can perform synthesis as well, like routing, compaction, silicon compilation, PLA generation, and compensation.
eSim: an integrated tool built from open source software such as KiCad, Ngspice, Verilator, Makerchip, GHDL, and OpenModelica. It is an EDA tool for circuit design, simulation, and analysis.
IRSIM: a tool for simulating digital circuits. It is a switch-level simulator, where transistors are treated as ideal switches. In this simulator, the circuit under simulation can be modified and then incrementally restimulated. It maintains the history of circuit activity and only restimulates the part of the circuit that deviates from its history.
Mosaic: Analogue integrated circuit designs can be created and simulated using the tool mosaic. It emphasizes a cutting-edge, user-friendly interface, immediate design feedback, design reuse, verification, and automation. Regardless of your internet connection, Mosaic will remain quick and accessible and synchronize your modifications when you reconnect.
Ngspice: An open-source mixed-signal SPICE simulator. ngspice has a command line input interface and plots the waveforms. This tool offers active development and improved stability. ngspice is based on three open-source free-software packages: Spice3f5, Xspice, and Cider1b1:
QUCS(Quite Universal Circuit Simulator): a well-advanced circuit simulator that supports all kinds of simulations like DC, AC, s-parameter, noise, transient analysis, etc. It allows importing existing SPICE models as well.
X Circuit: The schematic diagrams drawn from the schematic capture program do not produce an image that is suitable for publication. Engineers have to draw the schematic with the help of general-purpose drawing tools. It is a drawing tool that is specifically for circuits only. It can produce high-quality schematic diagrams and other figures that are suitable for publication purposes.
Xschem: a schematic capture program for VLSI and ASIC design.
XYCE: a SPICE-compatible software, written in C++ and using MPI (Message Passing Implementation). It also includes Trilinos ( Sandra’s open source library), which includes KLU direct solver and many more circuit-specific solvers.
ChipVault: an organization tool for HDL. It allows for hierarchical file navigation, sorting, and editing.
EDA Playground: a free web application for HDL (including Verilog, system Verilog, VHDL, and other HDLs) simulations and synthesis. It generates a browser-based waveform viewer after a successful simulation. It is easy to use because no download is required and code sharing is easy.
GHDL: translates VHDL files directly into machine code and hence faster compilation and analysis of code than any other interpreted simulator.
Icarus Verilog: a compiler for Verilog HDL as described in the IEEE-1364 standard. With the help of written Verilog code, it compiles the code into some target format. This tool supports a waveform viewer named GTKWave.
Migen: a python-based tool that applies advanced software concepts like OOPs, and metaprogramming in the VLSI design process and building complex digital hardware. It is a brand new programming language based on FHDL
Yosys: a synthesis tool that can handle Verilog code and can synthesize complex projects as well.
Fairly Good Router: a software for routing, based on Lagrange multipliers. It is an academic tool and it is based on similar routers used on industrial levels.
KLayout: KLayout is an editor that helps with the layout. It is also helpful in changing and creating GDS and OASIS files.
Magic: is considered one of the easiest tools for circuit layout. This tool supports LVS and DRC as well.
QRouter: a tool for routing based on the standard Lee maze routing algorithm. It supports LEF and DEF formats as input and output.
OpenSTA: is used to verify the timings of a circuit at the gate level.
OpenTimer: A high-performance, commercial-grade timing analysis tool. It helps IC designers with its interactive analysis to verify circuit timings. It supports both path-based and graph-based timing analysis. It is relatively a new tool that supports industry-standard format support like .lib, .v, .spef, and .sdc.
HiTas: Another tool for static timing analysis.
Netgen: is a verification tool for comparing a layout to a netlist. To ensure this physical verification and LVS is carried out. Netgen version 1.5 is considered a commercial-grade tool.
Dragon: is an effective tool for standard cell placement for variable and fixed die ASIC design.
Gdsfactory: Since gdsfactory is entirely written in Python, some Python concepts are necessary. It is built on top of KLayout, gdspy (Python library for producing GDSII files), and Phidl (Python module for GDS layout and cad geometry).
Alliance/Coriolis VLSI CAD Tools: Alliance / Coriolis is a free software toolchain for VLSI design. The input is HDL (Verilog or VHDL) and the output is GDSII, which is all set for ASIC manufacture.
Qflow: Provides a set of tools and methods to turn an HDL code (written in Verilog or VHDL) into a physical circuit. It is capable of handling sub-systems like host-to-device communication, signal processing, arithmetic logic unit, etc.
OpenLane: An automated VLSI design flow for digital synthesis. It is a collection of open-source tools. It performs all the tasks from RTL to GDS-II with the help of a predefined set of commands for design explanation and optimization. It has two modes.
OpenROAD: is a flow of open source tools for ASIC design. The whole flow is automated for digital SoC layout generation, focusing on the RTL-to-GDSII phase of system-on-chip design.
Silicon Compiler: automatically translates source code to hardware design. There are three steps.
IBTIDA:Fully open-source ASIC implementation of Chisel-generated System on a Chip
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