Jan 24, 2023

Mixed Signal SoC design Marathon using eSim & SKY130

Marathon Date : 23 Sept. - 8 Oct. 2022

The following submissions are adjudged as Outstanding, Excellent, Very good and Good by the FOSSEE and the VSD teams.

List of Outstanding Circuits:

# Participant Circuit InstituteGitHub 
1 Milad Vafaieenezhad Window Comparator Along with MOD-16 Counter for Counting Based Data Line Selection Operation Shahed University View Repo
2 Krunal Badlani Crack Sensing Circuit Indian Institute of Technology Hyderabad View Repo
3 Karuppusamy V Flash Type ADC Bannari Amman Institute of Technology View Repo
4 Inderjit Singh Dhanjal 32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology K. J. Somaiya College of Engineering View Repo
5 Tanay Das Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback Sikkim Manipal Institute of Technology View Repo
6 Jayanth Nedunuri Implementation of 4 bit Two Step Flash ADC Jyothishmathi institute of Technology and Science View Repo
7 Aishwarya Balkrishna Patil Design and Implementation of Automatic Security Monitoring System Kolhapur Institute of Technology’s College of Engineering, Kolhapur View Repo
8 Swagatika Meher 3-bit CMOS based TIQ comparator Flash ADC Odisha University of Technology and Research, Bhubaneswar, Odisha View Repo
9 Surya V 3-bit Flash ADC using ROM-based Encoder National Institute of Technology, Tiruchirapalli View Repo
10 Sanket M Mantrashetti Design of 8x8 SRAM based on 6T SRAM cell R. V. College of Engineering View Repo
11 Avishek Choudhary 10-bit C2C DAC Thapar Institute of Engineering and Technology View Repo
12 Nalinkumar S Implementation of Quadruple - Window Comparator Along with Prioritized MOD-16 Counter for Data Line Multiplexing Operation Madras Institute of Technology Campus, Anna University View Repo
13 Rubankumar D Astable Multivibrator Along with MOD-16 Counter for Counting Based Data Line Selection Operation Madras Institute of Technology Campus, Anna University View Repo
14 Vanshika Tanwar Implementation of 3 Bit Flash ADC performed in eSim Dronacharya Group Of Institutions, Greater Noida View Repo
15 Ravi Prakash Vishwakarma 8 Bit Counter/Ramp Type ADC Madan Mohan Malaviya University Of Technology View Repo
16 E Balakrishna Implementation of 4 Bit Flash ADC mixed signal circuit using 130nm performed in eSim Dronacharya Group of Institution, Greater Noida View Repo

Contact eSim-fossee:
For more information about the marathon, write to us at contact-esim[at]fossee[dot]in

Jan 19, 2023

Call for Papers - IEEE Special Issue of T-ED



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January 19, 2023 at 04:32PM
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#NIST and #Google to Create New Supply of #Chips for Researchers and Startups



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IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 
on Micro/Nanoelectronics, Devices, Circuits and Systems, 
29-31 Jan 2023 (Hybrid Mode)

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Date: 29 Jan 2023
Time:10:00AM to 06:00PM
 (UTC+05:30) 
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National Institute of Technology Silchar
Dept of ECE,
NIT Silchar Silchar, Assam India 788010
Building: ECE/CSE Building


National Inst of Technology - Silchar,
ED15 Kolkata Section Chapter NANO42
Co-sponsored by Dr. Trupti R. Lenka


Starts
Dec.1, 2022
Ends
Jan.28,2023

No Admission Charge
Register NOW

Agenda with following contribution Distinguished Lecturers: 
  • Anil Kottantharayil (anilkg@ieee.org)
  • Gananath Dash (gndash@ieee.org)
  • Ajit Kumar Panda (akpanda62@hotmail.com)
  • Manoj Saxena (msaxena@ieee.org)
  • Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
  • Samar Saha (samar@ieee.org)
  • Hiroshi Iwai (h.iwai@ieee.org)
  • Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
  • Pei-Wen Li (pwli@nycu.edu.tw)
  • Zhou Xing (EXZHOU@ntu.edu.sg)
  • Albert Chin (albert_achin@hotmail.com)
  • Mansun Chan (mchan@ust.hk)
  • Chao-Sung LAI (cslai@mail.cgu.edu.tw)
  • Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Jan 18, 2023

Neural networks and machine learning approach for compact modeling

[NN] Wang, Qiuwei, Mao Ye, Yao Li, Xiaoxiao Zheng, Jiaji He, Jun Du, and Yiqiang Zhao. "MOSFET modeling of 0.18 μm CMOS technology at 4.2 K using BP neural network." Microelectronics Journal (2023): 105678. DOI: 10.1016/j.sse.2022.108580

Highlights
  • The cryogenic characterization of SMIC CMOS technology at 4.2K is presented.
  • An optimization model VCCS is proposed to calibrate the cryogenic characteristics.
  • BP neural network is, for the first time, used in MOSFET modeling.
  • The cryo-model can be applied to SPICE simulator and assist in cryo-CMOS circuit design and simulation.
Fig: The structure of graph-based compact model of FinFET. The model receives the input features such as voltages, geometries, etc. as a vector and predicts the drain current (Ids) and its derivatives as output features.


[ML] Gaidhane, Amol D., Ziyao Yang, and Yu Cao. "Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach." Solid-State Electronics (2023): 108580.

Highlights
  • Developed a Graph-based compact model for FinFET.
  • Model implemented in Verilog-A for SPICE simulation.
  • Requires less number of model parameters and is computationally efficient than BSIM