[C4P] FLEPS 2022

Call for Papers

The IEEE International Conference on Flexible, Printable Sensors and Systems (FLEPS 2022) will be held in Vienna, Austria.

IEEE FLEPS 2022 is intended to provide a forum for research scientists, engineers, and practitioners throughout the world to present their latest research findings, ideas, and applications in the area of Flexible and Printable Sensors and Systems.

Topics of Interest

• Organic/Inorganic Electronic Sensors
• Emerging Materials for Flexible and Printable Systems
• Manufacturing Techniques
• High-throughput Printable Electronics
• Hybrid Flexible Sensors and Electronics
• Stretchable/Shrinkable Sensors and Electronics
• Soft/Smart Wearable and Implantable Sensing Systems
• Disposable/Reusable Sensors and Electronics
• Printed Large-Area Sensors and Systems
• Flexible or Printed Active and Passive Components (e.g. actuators, printed energy devices, smart labels, RFID etc.)
• Emerging applications of Flexible Electronics inc. IoT, smart cities etc.
• Simulation and Modelling
• Flexible/Printable Electronics in context with Circular Economy and green electronics

Publication of Papers: Presented papers will be included in the Proceedings of IEEE FLEPS 2022 and in IEEE Xplore pending author requirements being met. Authors may submit an extended IEEE FLEPS 2022 papers to the Special IEEE FLEX Journal Issue.

Exhibition & Patron Opportunities: The Conference exhibit area will provide your company or organization with the opportunity to inform and display your latest products, services, equipment, books, journals, and publications to attendees from around the world.

For further information, contact Coral Miller at Conference Catalysts, LLC.

[paper] Nanoscale InGaAs FinFETs

Jesús A. del Alamo1, Xiaowei Cai1,2, Xin Zhao1, Alon Vardi1, and Jesús Grajal3

Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport

51st European Solid-State Device Research Conference, Grenoble 2021

   
1: Microsystems Technology Laboratories, MIT, Cambridge (USA)
2: Analog Devices, Inc., (USA)
3: IPT Center, Universidad Politécnica de Madrid (SP)

Abstract: InGaAs is an attractive material for high-speed, high-frequency electronics and ultra-low-noise applications. A great effort has taken place recently towards the development of high-performance InGaAs MOSFETs with different geometries: planar MOSFETs, FinFETs and Nanowire MOSFETs. This exploration has uncovered a number of interesting device physics of relevance to the development of electronics based on other material systems. InGaAs is a narrow bandgap material. As such, it is prone to excess band-to-band tunneling at moderate voltages. Due to the floating nature of the InGaAs MOSFET body, holes generated by BTBT cannot escape from the body. Through a parasitic lateral bipolar transistor that is hiding inside the MOSFET, this results in excess off-state current, which compromises transistor logic operation. InGaAs also features a very small effective mass. This yields prominent ballistic effects in nanoscale devices. Towards studying this, we have developed a new technique to extract mobility and injection velocity in InGaAs MOSFETs in the presence of severe gate oxide trapping, as is the case in the high-k/InGaAs MOS system. In InGaAs FinFETs, we find a degradation in scattering limited mobility but an enhancement in ballistic mobility as the fin-width narrows. Also, the injection velocity shows no discernable fin width dependence. An important lesson from these studies is that long channel mobility measurements constitute a poor predictor of short-channel performance of InGaAs FinFETs.

Fig: Cross section of self-aligned InGaAs FinFETs on InP (left) along and (right) across the fin. The intrinsic channel is In_0.53Ga_0.47As and it is nominally undoped. These are double-gate devices.

Acknowledgment: Research sponsored by DTRA (#HDTRA 1-14-1-0057), NSF (E3S STC Award 0959514), MISTI, KIST and Lam Research. Devices fabricated in MIT’s Microsystems Technology Laboratories and EBL.

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[book] Future Ultra Low Power Electronics

Semiconductor Devices and Technologies for Future Ultra Low Power Electronics (1st ed.)

Nirmal, D., Ajayan, J., & Fay, P.J. (Eds.)

CRC Press. (2021).

DOI: 10.1201/9781003200987

Abstract: This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided. 

Contents:

Preface vii

Editors ix

Contributors xi

Chapter 1: An Introduction to Nanoscale CMOS Technology Transistors: A Future Perspective; pp: 1

Kumar Prasannajit Pradhan

Chapter 2: High-Performance Tunnel Field-Effect Transistors (TFETs) for Future Low Power Applications; pp: 29

Ribu Mathew, Ankur Beohar, and Abhishek Kumar Upadhyay

Chapter 3: Ultra Low Power III-V Tunnel Field-Effect Transistors; pp: 59

J. Ajayan and D. Nirmal

Chapter 4: Performance Analysis of Carbon Nanotube and Graphene Tunnel Field-Effect Transistors; pp: 87

K. Ramkumar, Singh Rohitkumar Shailendra, and V. N. Ramakrishnan

Chapter 5: Characterization of Silicon FinFETs under Nanoscale Dimensions; pp: 115

Rock-Hyun Baek and Jun-Sik Yoon

Chapter 6: Germanium or SiGe FinFETs for Enhanced Performance in Low Power Applications; pp: 129

Nilesh Kumar Jaiswal and V. N. Ramakrishnan

Chapter 7: Switching Performance Analysis of III-V FinFETs .; pp: 155

Arighna Basak, Arpan Deyasi, Kalyan Biswas, and Angsuman Sarkar

Chapter 8: Negative Capacitance Field-Effect Transistors to Address the Fundamental Limitations in Technology Scaling; pp: 187

Harsupreet Kaur

Chapter 9: Recent Trends in Compact Modeling of Negative Capacitance Field-Effect Transistors; pp: 203

Shubham Tayal, Shiromani Balmukund Rahi, Jay Prakash Srivastava, and Sandip Bhattacharya

Chapter 10 Fundamentals of 2-D Materials; pp: 227

Ganesan Anushya, Rasu Ramachandran, Raj Sarika, and Michael Benjamin

Chapter 11 Two-Dimensional Transition Metal Dichalcogenide (TMD) Materials in Field-Effect Transistor (FET) Devices for Low Power Applications; pp 253

R. Sridevi and J. Charles Pravin

Index pp: 289

[paper] Verilog-A Compact MTJ Model

Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan-Lucian Prejbeanu 

Fast Behavioral VerilogA Compact Model for Stochastic MTJ  

51st European Solid-State Device Research Conference; Grenoble 2021

  

CEA-Spintec (F)

Abstract: Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJ) are devices featuring stochastic properties. They are promising candidates for non-volatile memory or true random number generators. To design reliable hybrid CMOS circuits including STT-MTJs, one needs to use a compact model accounting for its stochasticity in the circuit simulations. This paper proposes a compact model that accurately mimics the MTJ stochastic switching behavior and meets the needs of fast execution time. The relevance of such a model together with its fast execution velocity are illustrated with a bitstream generator. 

Fig: Schematic representation of the implemented algorithm

Acknowledgement: This work is supported by the French National Research Agency in the framework of the "Investissements d’avenir” program (ANR-15-IDEX-02).