Oct 21, 2021

[paper] Charge-based Modeling of FETs

Jean-Michel Sallese 
Charge-based modeling of field effect transistors, Make it easy
Joint International EUROSOI and EuroSOI-ULIS Workshop (Sept.2020)
DOI: 10.1109/EuroSOI-ULIS53016.2021.956068
 
EDLab, EPFL,  Lausanne  (CH)
 
Abstract: In this presentation, we revisit some charge voltage dependencies for different architectures of field effect transistor, emphasizing on compactness and simplicity while maintaining a close link with physics, which makes these models predictive and accurate for general purposes of compact modeling.

Fig: The gm/I invariant versus the inversion coefficient IC. 
The operation modes of the MOSFET are clearly defined. 

Acknowledgements: I (JMS) would like to thank F. Jazaeri, C. Lallement, W. Grabinski, B. Iniguez and M. Bucher for their constructive interactions. 



Oct 20, 2021

[paper] CMOS floating-gate device for quantum control hardware

Michele Castriotta1, Enrico Prati2, Giorgio Ferrari1
Cryogenic characterization and modeling of a CMOS floating-gate device 
for quantum control hardware
preprint arXiv:2110.02315, 2021

1 Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano (I)
2 Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche (I)

Abstract - We perform the characterization and modeling of a floating gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and flexible cryogenic system for qubits control in large-scale quantum computers. The device stores onto a floating-gate node a non-volatile charge, which can be bidirectionally modified by Fowler-Nordheim tunneling and impact-ionized hot electron injection. These two injection mechanisms are characterized and modeled in compact equations both at 300 K and 15 K. At cryogenic temperature, we show a fine-tuning of the stored charge compatible with the operation of a precise analog memory. Moreover, we developed accurate simulation models of the proposed floating-gate device that set the stage for designing a programmable analog circuit with better performances and accuracy at a few Kelvin. This work offers a solution in the design of configurable analog electronics to be employed for accurately read out the qubit state at deep-cryogenic temperature.
Fig: Simplified layout of the p-type floating-gate device under test. The capacitive coupling to the floating-gate node  is realized with the poly 2 control gate.

Acknowledgments: This work was supported by QUASIX Grant from  Italian Space Agency. This work was partially performed at Polifab, the  micro- and nanofabrication facility of Politecnico di Milano

[paper] Parameter Extraction Approaches for Memristor Models

Dmitry Alexeevich Zhevnenko1,2, Fedor Pavlovich Meshchaninov1,2, Vladislav Sergeevich Kozhevnikov1,2, Evgeniy Sergeevich Shamin1,2, Oleg Alexandrovich Telminov1,2, and Evgeniy Sergeevich Gornev1,2
Research and Development of Parameter Extraction Approaches for Memristor Models
Micromachines 2021, 12, 1220. 
DOI: 10.3390/mi12101220
   
1 Moscow Institute of Physics and Technology, Moscow, Russia;
2 JSС MERI, Zelenograd, Russia

Abstract: Memristors are among the most promising devices for building neural processors and non-volatile memory. One circuit design stage involves modeling, which includes the option of memristor models. The most common approach is the use of compact models, the accuracy of which is often determined by the accuracy of their parameter extraction from experiment results. In this paper, a review of existing extraction methods was performed and new parameter extraction algorithms for an adaptive compact model were proposed. The effectiveness of the developed methods was confirmed for the volt-ampere characteristic of a memristor with a vertical structure: TiN/HfxAl1-xOy/HfO2/TiN.

Fig: Model VACs with different numbers of inhomogeneities: 
(a) four inhomogeneities; (b) no inhomogeneities.

Acknowledgments: This research was funded by the Ministry of Science and Higher Education of the Russian  Federation, grant number 075-15-2020-791. Authors thank the Institute of Microelectronics Technology and High-Purity Materials RAS for access to experimental data on the study of graphene oxide memristor switching cycles.


[paper] Compact model of 3D NAND

Kul Lee and Hyungcheol Shin
Distinguishing capture cross section parameter between 
in GIDL erase compact model and TCAD
Japanese Journal of Applied Physics. 2021 Oct 14.
 
ISRC and School of Electrical Engineering and Computer Science, Seoul National University, (KR)
 

Abstract: Compact model of 3D NAND enables simulation at circuit- or system- level. Although compact model for gate-induced-drain-leakage(GIDL)-assisted erase has been proposed in previous study, it is difficult to be used practically because it has not been properly validated. In particular, capture-cross-section (CCS) value that is far from the real value is used. Also, it doesn’t consider the latest device structure and its operation. In this paper, conventional GIDL-assisted erase compact model is validated using TCAD and improved more practically. It is confirmed that CCS should be distinguished in TCAD and compact model due to their different definition in each of them. Based on their physical differences, equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering tapered angle, single-side injection and word-line voltage is suggested.

Fig: Schematic cross section of 3D NAND string considering tapered angle. Double stacking and singe-side GIDL injection are assumed. It is assumed that the upper and lower stacks have the same dimension parameters.




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