[Data] CMOS SKY130 Cryo Primitives

Akturk, Akin, Li, Anhang, Saligane, Mehdi, Riem, Joseph, Adam, Gina, Hoskins,

Brian D, Shrestha, Pragya

CMOS SKY130 Primitives measured at cryogenic temperatures

NIST, (2023: Part of CHIPS METIS Data Collection)

Version: 1.1. Revised: 2024-03-27

DOI: 10.18434/mds2-2997 (Accessed 2026-01-03)

Abstract: SKY130 is an open source complementary metal oxide semiconductor (CMOS) technology manufactured by Skywater Technology (SKY) in its facility in Bloomington, Minnesota. Since it is an open source technology, there are no legal restrictions on its characterization, unlike in typical foundry semiconductor technologies. To facilitate the development of cryogenic electronics, this data set includes measurements of devices manufactured in SKY130 at low temperatures.

Fig: NIST Cryo Circuit Module Description

Name	File Type	Size
2997_README_v4.txt	Plain text	4.46 kB
ETest Tile.zip	Compressed file archive	3.81 MB
MPW-5 Test Tile.zip	Compressed file archive	39.5 MB

[paper] Channel-last GAA nanosheet oxide FETs

Fabia F. Athena, Xiangjin Wu, Nathaniel S. Safron, Amy Siobhan McKeown-Green, Mauro Dossena, Jack C. Evans, Jonathan Hartanto, Yukio Cho, Donglai Zhong, Tara Pena, Paweł Czaja, Parivash Moradifar, Paul C. McIntyre, Mathieu Luisier, Yi Cui, Jennifer A. Dionne, Greg Pitner, Iuliana P. Radu, Eric Pop, Alberto Salleo, H.-S. Philip Wong

Channel-last gate-all-around nanosheet oxide semiconductor transistor

arXiv:2512.21330v1 [cond-mat.mtrl-sci] 24 Dec 2025

1. Department of Electrical Engineering, Stanford University, Stanford (US)
2. Corporate Research, Taiwan Semiconductor Manufacturing Company, Ltd., San Jose (US)
3. Department of Chemistry, Stanford University, Stanford (US)
4. Department of Information Technology and Electrical Engineering, ETH Zurich (CH)
5. Department of Material Science and Engineering, Stanford University, Stanford (US)
6. Department of Chemical Engineering, Stanford University, Stanford (US)
7. Applied Energy Division, SLAC National Accelerator Laboratory, Menlo Park (US)
8. Institute of Metallurgy and Materials Science, Polish Academy of Sciences (PL)
9. Corporate Research, Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)

Abstract: As we move beyond the era of transistor miniaturization, back-end-of-line compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current (> 1mAμm) and low subthreshold swing (minimum of 63mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

Fig: Electrical performance of CL GAA FETs. (A) A SEM image of a representative device structure and (B) an AFM image of IWO deposited on a control sample show a uniform and smooth surface.  (C) IdVgs for a CL GAA FET with tch = 6nm measured at VDS = 0.05V and 1V. (D) IdVgs for a CL GAA FET with tch = 9 nm measured at VDS = 0.05V and 1V. Dual sweep shows very low hysteresis of about 0.038V at VDS = 0.05V.

Acknowledgment: Supported in part by SRC JUMP 2.0 PRISM and CHIMES Center, Stanford Differentiated Access Memory (DAM), SystemX Alliance, Stanford NMTRI, TSMC-Stanford Joint Development Project (P.C.M.). Part of this work was performed at Nano at Stanford (RRID SCR 026695). Authors acknowledge help and support for the AFM measurements from Christina Newcomb. Stanford authors thank MSS USA Corp. for high quality TEM sample preparation and examination and Dr. David Fried of Lam Research for providing access to Coventor SEMulator3D for process simulation. Use of the Stanford Synchrotron Radiation Lightsource at SLAC National Accelerator Laboratory is supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences under Contract No. DE-AC02-76SF00515. Y.C. acknowledges the support from the Japan Society for the Promotion of Science (JSPS) overseas research fellowship. J.A.D., A.M.G., and P.M. acknowledge the financial support from the U.S. Department of Energy Office of Science National Quantum Information Science Research Centers as part of the Q-NEXT center. Y.C. and F.F.A. would like to thank the support from the Stanford Energy Postdoctoral Fellowship and Precourt Institute for Energy.

[paper] Cryogenic CMOS Device Modeling

Zhidong Tang, Zewei Wang, Yumeng Yuan, Chang He, Xin Luo, Ao Guo, Renhe Chen, Yongqi Hu, Longfei Yang, Chengwei Cao, Linlin Liu, Liujiang Yu, Ganbing Shang, Yongfeng Cao, Shoumian Chen, Yuhang Zhao, Shaojian Hu, and Xufeng Kou

Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform 

for Reliable Cryogenic IC Design

IEEE JEDS, vol. 13, pp. 117-127 (2025)

DOI: 10.1109/JEDS.2025.3542589

1. ShanghaiTech University, Shanghai (CN)
2. University of Chinese Academy of Sciences, Beijing (CN)
3. Shanghai IC Research and Development Center, Shanghai (CN)
4. Huali Microelectronics Corporation (HLMC), Shanghai (CN)
5. School of Integrated Circuits, Tsinghua University, Beijing (CN)

Abstract: This paper outlines the establishment of a generic cryogenic CMOS database in which key electrical parameters and transfer characteristics of the MOSFETs are quantified as functions of device size, temperature, and frequency responses. Meanwhile, a comprehensive device statistical study is conducted to evaluate the influence of variation and mismatch effects at low temperatures. Furthermore, by incorporating the Cryo-CMOS compact model into the HLMC process design kit (PDK), the cryogenic 4Kb SRAM, 5-bit flash ADC and 8-bit current steering DAC are designed, and their performance is readily investigated and optimized on the EDA-compatible platform, hence laying a solid foundation for large-scale cryogenic IC design.

FIG: Schematic of the solid-state based quantum computer architecture 

with integrated quantum control system in a cryogenic environment.

Acknowledgments: This work was supported by the National Key R&D Program of China (2021YFA0715503, 2023YFB4404000), National Natural Science Foundation of China (92164104), the Strategic Priority Research Program of CAS (XDA18010000), Shanghai Rising-Star Program (21QA1406000) and the Open Fund of State Key Laboratory of Infrared Physics.

[paper] Efficient Long-Channel MOSFET Model

Ananda Sankar Chakraborty

Efficient Long-Channel MOSFET Model 

with SPICE-enabled Lambert W Function for Universal Application

Silicon (2025): 1-10; DOI 0.1007/s12633-025-03576-1

1 ETCE, Indian Institute of Engineering Science and Technology, Shibpur (IN)

Abstract: A novel, accurate charge-based MOSFET long-channel computational model is presented, which is portable and can be used across the electrical engineering domains ranging from sensing to power electronics, both under sub-threshold as well as super-threshold regime of MOSFET operation. The proposed physics-based model can be universally used to any long-channel MOS-transistor, as it does not depend on any empirical factor and features extremely good computational efficiency. The model uses a novel two-step charge linearization, resulting into accurate drain current and charge model – valid for both the subthreshold and super-threshold regime of long-channel MOSFET operation. Another salient feature of the proposed model is a novel SPICE-compatible numerical solution strategy for the principal branch of the Lambert W function (W0(x) for {x ∈ R | x ≥ 0}). The algorithm is faster than present industry standard implementations, computationally efficient, accurate with maximum percentage error≈10−14% and therefore may be incorporated in a SPICE engine for electrical design and optimization. The proposed computationally efficient long channel MOSFET model is validated against thorough TCAD simulations upto the fourth derivative and has been found to have fast convergence along with much higher degree of accuracy compared to existing MOSFET models.

FIG: Bulk-MOSFET structure: its current (I_DS) and conductance (g_DS) vs Drain Voltage (V_DS)

(Line: proposed model, symbol: TCAD)

[paper] Bioinspired Phototransistor

Ruyue Han, Dayu Jia, Bo Li, Shun Feng, Guoteng Zhang, Yun Sun, Zheng Han, Chi Liu, Hui-Ming Cheng and Dong-Ming Sun

Bioinspired phototransistor with tunable sensitivity for low-contrast target detection

Light Sci Appl 15, 12 (2026) DOI: 10.1038/s41377-025-02051-1

Shenyang National Laboratory for Materials Science, Institute of Metal Research, CAS, Shenyang (CN)
School of Materials Science and Engineering, University of Science and Technology of China, Shenyang (CN)
School of Information Institution, Liaoning University, Shenyang (CN)
State Key Laboratory of Quantum Optics and Quantum Optics Devices, Shanxi University, Taiyuan (CN)
Collaborative Innovation Center of Extreme Optics, Shanxi University, Taiyuan (CN)
Liaoning Academy of Materials, Shenyang (CN)
Faculty of Materials Science and Engineering, Shenzhen Institute of Advanced Technology, CAS, Shenzhen (CN)

Abstract: Accurate recognition of low-contrast targets in complex visual environments is essential for advanced intelligent machine vision systems. Conventional photodetectors often suffer from a weak photoresponse and a linear dependence of photocurrent on light intensity, which restricts their ability to capture low-contrast features and makes them susceptible to noise. Inspired by the adaptive mechanisms of the human visual system, we present a molybdenum disulfide (MoS2) phototransistor with tunable sensitivity, in which the gate stack incorporates a heterostructure diode—composed of O-plasma-treated MoS2 and pristine MoS2—that serves as the photosensitive layer. This configuration enables light-intensity-dependent modulation of the diode’s conductance, which dynamically in turn alters the voltage distribution across the gate dielectric and transistor channel, leading to a significant photoresponse. By modulating the gate voltage, the light response range can be finely tuned, maintaining high sensitivity to low-contrast targets while suppressing noise interference. Compared to conventional photodetectors, the proposed device achieves a 1000-fold improvement in sensitivity for low-contrast signal detection and exhibits significantly enhanced noise immunity. The intelligent machine vision system built on this device demonstrates exceptional performance in detecting low-contrast targets, underscoring its promise for next-generation machine vision applications.

FIG: Performance of tunable-sensitivity phototransistor array. (a) Optical image of a 3 × 3 phototransistor array (scale bar: 200 μm). (b) Magnified image of an individual sensor unit (scale bar: 10 μm). 

(c) IDS−VGS curves of the 9 phototransistors in dark and under 516-nm light at VDS = 0.1 V. 

Acknowledgements: This work was supported by the National Key Research and Development Program of China (2021YFA1200801), the National Natural Science Foundation of China (No. 62304226, 52188101, 62450124, 62125406), the China Postdoctoral Science Foundation (2024T170946, 2023M733574), the Excellent Youth Fund Project of Liaoning Province (2023JH3/10200003), the Outstanding Youth Fund Project of Liaoning Province (2025JH6/101100015), the Special Projects of the Central Government in Guidance of Local Science and Technology Development (2024010859-JH6/1006), the Special Research Assistantship Project of the Chinese Academy of Sciences (E455L502), the China Postdoctoral Science Foundation under Grant Number GZB20230776, the Liaoning Provincial Key Laboratory of Public Opinion and Network Security Information System (d252453002), the Artificial Intelligence Technology Innovation Project of Liaoning Province (Grant No. 2023JH26/10300019), the Young Top-notch Talents of the National High-level Talent Special Support Program, the basic scientific research project of universities funded by the Liaoning Provincial Department of Education (LJ212510140016) and the Liaoning Province High-quality Industry-University Cooperation and Collaborative Education Project (241201160090747). The authors gratefully acknowledge Dr. Bing Yang and Dr. Honglei Chen from the Institute of Metal Research for their valuable support in HRTEM-EDS characterization.