[Internship] Open Source CAD Design Flows

A great opportunity at CEA-Leti in Grenoble, France! This 6-month internship focuses on open source CAD design flows with related PDK, targeting final-year engineering or Master 2 students with an analog/digital design profile.

Description

Are you eager to explore the backstage of microelectronics and learn how to turn a circuit design into a chip ready for fabrication? This internship invites you to take on an exciting challenge: setting up and running a complete open source design flow on related process technology, using an existing SAR ADC design as a motivating example.

The core mission is not to redesign the ADC, but to master the flow that makes such a design possible: installing the tools, configuring the PDKs, and validating each step of the process. How do you configure and launch open source EDA tools? How do you run simulations, placement and routing, and physical verification checks? What are the strengths and limitations of open source technologies in microelectronics design IC? You will be encouraged to explore these questions and propose your own answers.

• Starting date: Spring 2026
• Duration: 5-6 months
• Location: Grenoble, France

Your main tasks will include:

• Installing and configuring the open source design environment (PDK, EDA tools, automation scripts).
• Running the design flow on an existing SAR ADC as a case study.
• Carrying out simulation, synthesis, place-and-route, and DRC/LVS verification.
• Identifying bottlenecks and documenting reproducible solutions.

The student will be supported by an experienced team, with close mentoring and external collaborations to enrich your learning. He won't be left alone with the complexity of the flow – he will be guided, encouraged to test, and empowered to take initiatives. Indicative time allocation: ~30% installation and flow automation, 30% simulation and verification, 30% design adaptation, 10% analysis and scientific dissemination.

Candidate Profile

You are a master's student in microelectronics, embedded systems, or related fields. You have basic knowledge in digital/analog design, simulation, or VLSI concepts. You have basic experience writing scripts in bash/csh and are comfortable working in a Linux environment.

Supervisors: 

Youcef Fellah & Guillaume Regis

To apply, please contact: <youcef.fellah@cea.fr>

[mos-ak] [C4P] ICMTS 2026 Mar. 23-26, 2026 in Matsue, Japan

IEEE International Conference on Microelectronic Test Structures

Mar. 23-26, 2026 at Kunibiki-Messe Convention Center in Matsue, Japan

ICMTS 2026 Call for Papers

Abstract submission deadline: Nov 15, 2025

Looking for the best opportunity to present and discuss your ideas and results about test structures, measurements, and characterization? This is your chance! Join the 38th ICMTS conference.

This conference is co-sponsored by the IEEE Electron Devices Society. All presented papers will be submitted for potential inclusion in IEEE Xplore®. Original papers presenting new developments in topics relevant to ICMTS, include but not limited to test structures, measurements, and results, as outlined below. This one-track technical program will award a Best Paper that will be voted on by the Technical Program Committee. In addition, Tutorial Short Course will precede the main conference while several of the best measurement, equipment design, and manufacturing experts, will participate in the equipment exhibition and presentations.

• Design
• Methodologies, Verification
• Within-die circuits for process characterisation/monitoring
• Design enablement, characterisation and validation of digital and analog libraries
• Devices and Circuit Modelling
• Measurement techniques
• DC, AC and RF measurements: setup, test and analysis
• Reliability test - including thermal stability, failure analysis etc.
• Statistical analysis, variability, throughput increase, smart test strategies
• Use of machine learning and AI in analysis of data sets - parameter extraction etc.
• Wafer probing, within-die measurements, in-line metrology
• Throughput, testing strategies, yield enhancement and process control tests
• Applications
• Emerging memory technologies (single cell, arrays, and application in neural networks)
• Emerging transistor technologies for digital/analog/power applications
• Photonic devices - silicon integration, new displays (OLED, μ-displays)
• Flexible electronics and sensors (organic and inorganic materials)
• M(N)EMS, actuators, sensors, PV cells and other emerging devices

The author's abstract submission consists of up to four pages in PDF format (font-embedded). The first page should include a title, a 50-word summary, author name(s), full address, contact number and e-mail of the lead author, and any preference for oral or poster session presentation. The body of the abstract should consist of one page of text (800 to 1000 words) and up to two pages of major figures and tables.

The selection process will be based on the technical merit and will be highly weighted in favour of abstracts with high test structure content, giving a clear illustration of the test structure and including measurements and data analysis.

Abstract submission deadline: Nov 15, 2025

Notice of paper acceptance will be sent to the selected authors by Jan 17, 2026, with instructions for the expanded manuscript preparation for the conference proceedings. The deadline for submission of the final, camera-ready paper will be Feb 17, 2026.

Please join the ICMTS group at 

https://www.linkedin.com/groups/3804498    

if you have interest in all things, test and measurement.

Details of the venue, hotel, conference registration, etc. are available here.

If you have any questions, please contact the Technical Program Chair:

• Tatsuya OHGURO, tatsuya.ooguro@toshiba.co.jp
• Kejun XIA, kejun.xia@gmail.com

[mos-ak] [Special Issue] 7th International Sino MOS-AK Workshop

Special Issue on the 7th International Sino MOS-AK Workshop

Jun Zhang, Wladek Grabinski, Yuehang Xu (editors)

Int JNM, 38: e70114.

First published: 07 September 2025

https://doi.org/10.1002/jnm.70114

1. College of Integrated Circuit Science and Engineering, Nanjing University, Jiangsu (CN)

2. MOS-AK and GMC Consulting (CH)

3. School of Electronic Science and Engineering, Uni. Chengdu, Sichuan (CN)

As device structures become increasingly complex, with the continuous emergence of novel materials, unconventional architectures, and new physical phenomena, the coupling of multiple physical domains, including thermal, electrical, and optical effects, is becoming ever more prevalent. At the same time, rising development and manufacturing costs place additional demands on modelers to deliver representations that are both accurate and computationally efficient across the entire chain from device physics to circuit behavior. Modeling serves two complementary purposes: Theoretical models provide insight into the operating principles of devices, while also guiding design optimization and enabling engineers to fully exploit intertwined physical effects. Analytical modeling, however, often requires careful trade-offs among accuracy, generality, and simplicity. Models must be predictive enough to inform design while offering meaningful physical insight. In modern semiconductor devices, which often feature three-dimensional geometries, solving the coupled semiconductor physics equations analytically is extremely challenging or even impossible. Closed-form solutions are typically unattainable, so judicious simplifications are necessary to ensure that models remain tractable and practically useful.

The papers in this Special Issue address these challenges by balancing physical fidelity with computational efficiency. They deepen our understanding of device physics while providing models that are both insightful and practical, with applications spanning cryogenic electronics, wide-bandgap devices, and radiation-hardened systems.

Su et al. present a charge-based analytical model for bulk MOSFETs, that is, valid down to 10 mK. Their work clarifies the interface-trap-dominated mechanisms that lead to threshold voltage divergence between NMOS and PMOS devices and quantifies significant analog parameter enhancements, including a 73% increase in PMOS cutoff frequency at 4 K. These findings are essential for quantum-control electronics. Complementing this, Mao et al. provide a comprehensive review of four physics-based compact models for GaN HEMTs, namely MVSG, ASM HEMT, EPFL, and QPZD. They analyze how each model addresses challenges such as trapping effects, self-heating, and process variability, and highlight emerging opportunities for combining physical models with machine learning to accelerate parameter extraction and quantify uncertainties. In the area of radiation-tolerant electronics, Xu et al. introduce a machine-learning approach using an ant-colony-optimized neural network. By adaptively sampling critical waveform regions, their method achieves an RMS error of only 0.82% in predicting single-event transient currents, surpassing the fidelity limits of traditional double-exponential pulse models and enabling high-precision radiation effect simulation for aerospace applications. Meanwhile, Deng et al. demonstrate a practical strategy for AI-assisted SPICE integration. They employ geometry-parameterized scaling laws for spiral inductors and machine-augmented Power MOS trans-conductance models to accelerate parameter extraction by an order of magnitude while preserving full SPICE compatibility. This approach significantly streamlines industrial design workflows.

Collectively, these contributions point to a trend toward physics-informed, data-driven co-design methodologies. By combining rigorous physical insight with computationally efficient, machine learning–aware workflows, they enable robust optimization of devices and circuits across a wide range of applications, from quantum interfaces to aerospace systems.

Future research should prioritize the development of standardized interfaces between AI tools and physical models, the extension of models to three-dimensional integrated wide-bandgap architectures, and the establishment of co-design frameworks for emerging ultra wide–bandgap materials capable of operating in environments ranging from near-zero Kelvin to orbital radiation conditions. We sincerely thank all authors for their outstanding contributions, which have advanced the frontier of semiconductor modeling science.

[Read more...]

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[Deadline] extended to Oct.15 2026

10th IEEE Electron Devices Technology and Manufacturing

(EDTM 2026) Conference

https://ieee-edtm.org/

March 1-4, 2026 Penang, Malaysia 

EDTM2026 paper submission date has been extended to 15th October 2025

Submit your papers today in any of the 13 tracks and see you in Penang, Malaysia from 1st - 4th March 2026.

• Contributed papers will be judged for the best paper award for each technical track
• Each track will have Invited Speakers. Meet prominent Plenary and Keynote Speakers from Industry and academia for research, networking, innovation and commercialization purposes
• Exhibition and sponsorship opportunities to showcase breakthrough technology
• Extended versions of accepted papers to be published in 
• EEE Transactions on Materials for Electron Devices (T-MAT) and 
• Journal of IEEE Electron Devices Society (JEDS)

[workshop] Advances in Semiconductor and Emerging Devices for Chip Design

5-Day Online International Workshop on

Recent Advances in Semiconductor and Emerging Devices for Chip Design

Oct. 6-10, 2025

Organized by the Department of Electronics, Dhanamanjuri University (DMU), Manipur,

in Collaboration with IEEE Silchar Subsection

Upcoming 5-Day International Workshop on “Recent Advances in Semiconductor and Emerging Devices for Chip Design” (6–10 October 2025) organized by Dhanamanjuri University (DMU) Manipur, in collaboration with IEEE Silchar Section. This unique event, led by Dr. Khoirom Johnson Singh, Ph.D. and his dedicated team, brings together global experts from India, Europe, and beyond. Register Online

With speakers covering topics from GaN devices and memristors to cryogenic CMOS, nanosheet FETs, biomedical circuits, and spintronics for novel computing, this workshop will serve as a melting pot of ideas, a platform for young researchers and students to learn, question, and seed new collaborations.

Education equips young minds with the foundations of knowledge, preparing them to understand technological advancements and their role in shaping society. Yet, in research, knowledge alone is not enough. To truly innovate, we must disseminate our work, engage with peers, and foster collaborations across disciplines and borders. This is where the seeds of research truly take root and grow.

Collaboration is more than sharing data or co-authoring papers. It is about bringing together diverse perspectives, connecting physics with engineering, theory with experimentation, and academia with industry. Interdisciplinary approaches not only accelerate breakthroughs, but also open new directions that no single researcher could achieve alone.

Register Online...