MEMUNITY Workshop "Reliability, Testing, and Characterization of Micro Systems"

Registration for the MEMUNITY Workshop "Reliability, Testing, and Characterization of Micro Systems" is now open! To register, please send an email with the names of all participants and company contact information to info@memunity.org by August 31st.

The workshop will take place on Wednesday, September 15th, 2010 from 9 am to 5 pm at IVAM e.V. Fachverband für Mikrotechnik in Dortmund, Germany (Emil Figge Str. 76, 44227 Dortmund, Germany). Technical presentations and discussions will be held by industry experts including Fraunhofer ENAS, IMEC, Cascade Microtech, Inc., Polytec, IMMS, aixACCT, Agilent, Solidus Technologies, Process Relations, Fraunhofer IWMH, ELMOS, and IHP. The full agenda can be downloaded from www.memunity.org or www.ivam.de. Please note, the workshop is free of charge!

For further information contact Frank-Michael Werner

SPICE and FastSPICE, Podcast from DAC

In case you didn’t visit DAC 47 in Anaheim, California to see the SPICE and FastSPICE panel session, you can still listen to Daniel Payne moderating the three panelists:

• Pierluigi Daglio – STMicroelectronics, Agrate, Italy
• Aaron Barker – Oracle, Broomfield, CO
• Jin-Qin Lu – Atheros Communications, Inc., Santa Clara, CA

(from left to right) Daniel Payne, Aaron Barker, Jin-Qin Lu, Pierluigi Daglio
[source]

IBM INDIA: Job Opportunities

IBM INDIA SEMICONDUCTOR RESEARCH & DEVELOPMENT CENTER(SRDC)

IBM SRDC develops all of IBM’s semiconductor technologies including SOI, Bulk CMOS, RFCMOS, HV CMOS, and SiGe HBT BiCMOS Technologies. The IBM SRDC at Bangalore is responsible for developing compact models and process design kits (PDK), leading edge computational lithography, functional characterization support and theory, designs, models for nanoscale devices.

Job Opportunities

COMPACT MODELING ENGINEER: Work in a very challenging environment with experienced device modelers and RF circuit designers. The responsibilities will include development of compact models for both active (FET, BJT) and passive (diodes, varactors, MIMCAP, inductors) devices in mixed signal, and RF technologies. Working closely with device engineers to define parameter targets and with foundry clients to resolve any modeling issues in design. Defining test programs for DC and RF device measurement and characterization. Use of software such as ICCAP to extract parameters for BSIM, PSP or other models. Strong semiconductor device physics background and previous experience of device modeling / characterization / design are required. The candidate should have a MS degree in Electrical Engineering / Physics with at least 3 years of experience in device modeling related work or a PhD degree in Electrical Engineering.

DESIGN AUTOMATION TECHNICAL LEAD: An experienced professional to lead the PDK Design Automation (DA) team. Bangalore team is responsible for device model and enablement for process development kit (PDK) for some of the key technologies of IBM's specialty foundry business. The person leading the DA team will be part of a highly talented team with global experience and should be able to maintain the best-in-class PDK quality that IBM is known for. The minimum experience for this position should be at least 6-7 years of industry experience in the area of Design Automation (Parasitic extraction, Final kit Testing, DRC code generation, Pcell development) in the RF, analog & mixed signal environment. The ideal candidate should be able to lead a team of 10+ engineers, technically mentor and guide on project deliverables, can effectively collaborate with different GEO's like US & France and interface with Foundry customers on Design Automation related issues. Minimum academic qualification should be Master's with 6-7 years or PhD with 3+ years of relevant experience. Exceptional candidates with outstanding credentials with Bachelor's degree with 8-9 years of experience may also be considered. Previous management experience is a plus.

For more details visit website : www.ibm.com
Send resume to anibandy@in.ibm.com

Job offers in LinkedIn

Remember: this is only a copy of a post in LinkedIn. We're not associated in any way to any of them...

Senior Research & Development Engineer
Group: Silicon Engineering Group
Location: Hyderabad, India
Contact @ akshat.kumar@synopsys.com

This position is for a senior R&D engineer who will join the TCAD team and work on the development and maintenance of state of the art back-end/interconnect analysis tools. Primary responsibilities include designing and developing physical models and numerical algorithms and implementing these algorithms in general purpose multidimensional semiconductor back-end/interconnect simulators in C++.
- PhD in a relevant field.
- Exp. with semiconductor back-end/ interconnect simulation tools focusing on one or, more of electrical, thermal, mechanical, and reliability analysis, numerical methods for solving partial differential equations (finite element and/or finite volume method), mesh generation.
- ~3 to 5 years of experience as a developer on large Finite Element Analysis simulators in either a commercial, or industrial/research lab setting. Prior experience with Synopsys TCAD tools is strongly preferred.
-Software development experience in C++ and preferably Tcl/Tk.
-Good communication skills and the ability to work within a team are essential.

some reading for summertime

Appl. Phys. Lett. 96, 253301 (2010); doi:10.1063/1.3453661 (3 pages)

Current bistability and carrier transport mechanisms of organic bistable devices based on hybrid Ag nanoparticle-polymethyl methacrylate polymer nanocomposites

Won Tae Kim, Jae Hun Jung, Tae Whan Kim, and Dong Ick Son

Abstract:The current bistability and the carrier transport mechanisms of organic bistable devices (OBDs) using Ag nanoparticle-polymethyl methacrylate (PMMA) nanocomposites have been investigated. Current-voltage measurements at 300 K on the Al/Ag nanoparticles embedded in the PMMA layer/indium-tin-oxide devices exhibit a current bistability with an ON/OFF ratio of 10³. Write-read-erase-read sequence results demonstrate the switching characteristics of the OBD. The cycling endurance number of the ON/OFF switching for the OBD is above 7×10⁴. The current bistability and carrier transport mechanisms of the OBD fabricated utilizing hybrid Ag nanoparticle-PMMA polymer nanocomposites are described on the basis of the experimental data.

 Physica E: Low-dimensional Systems and Nanostructures

Quantum transport modeling of defected graphene nanoribbons 

 I. Deretzis, G. Fiori, G. Iannaccone, G. Piccitto and A. La Magna


Abstract: We study backscattering phenomena during conduction for graphene nanoribbons of μm lengths, from single vacancy scatterers up to finite defect concentrations. Using ab initio calibrated Hamiltonian models we highlight the importance of confinement and geometry on the shaping of the local density of states around the defects that can lead to important alterations on the transport process, giving rise to impuritylike conduction gaps in the conductance distribution. Within a statistical analysis of finite defect concentration we show that conductance degradation can become very important.




 Solid-State Electronics
The spatial origin of current noise in semiconductor devices in the framework of semiclassical transport
C.E. Kormana, B.A. Noaman

Abstract: A new model to semiconductor device electronic noise is presented in the framework of semiclassical transport theory. The salient feature of this model is that it connects the current noise characteristics directly to the physics of scattering of the semiclassical transport theory and makes no additional assumption regarding the nature of noise. Employing this approach, this work investigates the spatial origin of the current noise across two semiconductor structures. In this approach the terminal current noise is directly related to carrier scattering inside the device, which is accounted for in the Boltzmann transport equation (BTE), without the need to add Langevin noise terms to the calculations. Accordingly, it utilizes the well-established spherical harmonics expansion (SHE) technique to solve the BTE, and it combines analytical and numerical methods, in contrast with the Monte Carlo (MC) approach that employs ensemble averages of randomly generated events. The model leads to the solution of a time-dependent transient solution of the BTE with special initial and Ohmic boundary conditions that is solved in the frequency domain to directly compute the terminal current noise spectral density. It is also shown that with this approach the Nyquist theorem under thermal equilibrium conditions is recovered.

 

The Ten Commandments for Effective Standards

The Ten Commandments for Effective Standards:

Practical Insights for Creating Technical Standards

Karen Bartleson (Author)

Publisher: Synopsys Press (May 7, 2010)
Language: English
ISBN-10: 1617300020
ISBN-13: 978-1617300028

About the Author:
Karen Bartleson has three decades' experience in the computer chip industry. She is known for her work in the area of standards for electronic design automation, and is also one of the pioneers into social media in her industry, including Twitter. She is the author of "The Standards Game," a blog focused on the standards arena. Karen holds a BSEE from California Polytechnic State University, San Luis Obispo, California, and was the recipient of the Marie R. Pistilli Women in Design Automation Achievement Award in 2002. Her Twitter handle is @karenbartleson. --This text refers to the Paperback edition.

MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

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MOS-AK/GSA ESSDERC/ESSCIRC Workshop: http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php

Tentative list of the invited speakers (alphabetic order):
   * Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
   * Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
   * Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
   * Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
   * David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
   * Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
   * Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
   * Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.

For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.

[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

MOS-AK/GSA ESSDERC/ESSCIRC Workshop: http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF
Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php

Tentative list of the invited speakers (alphabetic order):
* Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
* Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
* Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
* Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
* David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
* Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
* Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
* Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1 http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17 http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
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SPICE update from Mentor

Daniel Payne talked with See-Mei Chan, Technical Marketing Manager at Mentor Friday morning because they couldn’t connect in Anaheim earlier this week. Daniel wanted to better understand what is new with Eldo, the SPICE circuit simulator at Mentor.

Read more in June 18th, 2010 post by Daniel Payne in Analog Fast SPICE, DAC 2010, Fast SPICE, SPICE circuit simulation.

News and Views: Nature Nanotechnology

A. M. Ionescu

Electronic devices: Nanowire transistors made easy

Nature Nanotechnology, vol. 5, iss. 3, pp. 178 – 179, March 2010

Figure (a) A junction FET is turned on in the (strong) inversion condition, when a channel of minority carriers is formed just under the gate, and junction barriers to their flow are reduced. The off state of the junction FET corresponds to high junction barriers and the suppression of the inversion channel. The horizontal red line shows the bottom of the depletion region, and the slanted red lines indicate the limits of the depletion region controlled by the gate. (b) In contrast, the on state of a junctionless FET is obtained in 'flat band' conditions, with majority carriers travelling through a highly doped film. The device (which requires a thin-film silicon-on-insulator substrate) turns off when the gate-controlled depletion extends over the whole film. Both devices operate with the source grounded and a positive potential applied to the drain. Vt denotes the threshold voltage (positive for the n-type devices). Similar descriptions apply to the operation of complementary p-type FETs. Blue and red colours depict electron and hole doping respectively, with a darker colour indicating heavier doping. The white regions correspond to the depletion regions, and the green colour represents the gate oxide.

References

1. Lilienfeld, J. E. Method and apparatus for controlling electric current. US patent 1,745,175 (1925)
2. Shan, Y., Ashok, S. & Fonash, S. J. Appl. Phys. Lett. 91, 093518 (2007)
3. Lin, Y.-W., Marek-Sadowska, M., Maly, W., Pfitzner, A. & Kasprowicz, D. in Int. Conf. Computer Design 557–562 (IEEE, 2008)
4. Soree, B. & Magnus, W. in 10th Int. Conf. Ultimate Integration of Silicon 245–248 (IEEE, 2009)
5. Lee, C. W. et al. Appl. Phys. Lett. 94, 053511 (2009)
6. Colinge, J. P. et al. Nature Nanotech. 5, 225–229 (2010)
7. Tsutsui, K. et al. in Int. Workshop Nano CMOS 56–68 (IEEE, 2006)
8. Aoyama, T. et al. in Int. Workshop Junction Technol. 110–115 (IEEE, 2009)

An interesting (educative?) post in EDN by Paul Rako :

Op-amp Spice macro-models article from Intersil

June 16, 2010

Former EDN analog editor Bill Schweber has published a good article from Tamara Schmitz and Jian Wong about developing Spice macromodels for voltage-feedback op-amps. Part 1 (pdf), and part 2 (pdf). All the youngsters like to use Spice for op-amp circuit design but I am more like Bob Pease and Jim Williams, you have to build the circuit to know what is going on. I will never forget being perfectly happy with a Spice run, until I built the circuit and realized that the quad op amp was running way too hot. I did not notice the power consumption of each of the amps was about ¼ W. That was a newbee mistake, sure, but even if Spice does not lie, it is the product of digital and software minds, so rather than flashing a big red sign that warns you that you are going to burn up the quad op amp, they just require you to define a power variable and display it and then print the result in the same tiny test and the blizzard of other information. Then software people smile and fold their arms and tell us everything is our fault, since the information was right there if only we asked for it.  The one thing about analog is that is has a sense of importance. That’s why steering wheels and shift levers are big and prominent and radio treble controls are tiny little buttons. If software people designed cars everything would be a tiny little icon and the crash warnings would be in 10-point text.
So anyway, Spice does not necessarily lie like Bob Pease says, but I guarantee you that if you give it poor models it will give you the wrong answer. This is the big hassle with op amp models. Some of them, like the old National Semi Comlinear models (pdf) published by Mike Steffes before he left for Burr Brown and now Intersil were essentially transistor-level models. An IC designer could infer the design of the part from them. Mike told me that he knew that, but it was just so important to give an accurate model that he felt he had to release those great models. If someone wanted to copy the circuits, well, they had a lot more work to do-anyone can de-cap an op amp and reverse engineer it in a day. That still does not give you the process or the testing regime or the design secrets and tricks.
That is why this Intersil article is so important. Anything that helps you make good models is important in a world where kid engineers trust a computer rather than a breadboard. The article give some history of op amp models and that will tip you off as to what you can expect from a simulation. If the model you use does not model for 1/f noise, and most vendor models do not, you cannot get a meaningful simulation of low-frequency noise performance of the circuit. If the model does include flat-band noise and you are designing and ac-coupled video circuit, well that is fine for your needs. I have yet to see a Spice op-amp model that accurately tells you what happens if you bang the output into the rails and saturate the transistors. I will ask Mike Steffes if his old Comlinear models would do that, and leave a comment.

Modeling The Bipolar Transistor (Book)

Modeling The Bipolar Transistor (*)
By Ian Getreu

(2009; Paperback, 286 pages)

The book describes the bipolar transistor model and parameter measurement techniques for the SPICE circuit simulator. Originally published by Tektronix in 1974, this is a slightly modified revision republished in 2009 by the original author.

Read the review by Colin McAndrew

(*) There is a $4.00 discount if people order it by June 30 - use the coupon code: SUMMERREAD305.

IEEE Awards 2010

Takayasu Sakurai, has got the 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, for pioneering contributions to the design and modeling of high-speed and low-power CMOS logic circuits.

Note that this is not compact modeling, but his alpha power law model has had a big impact!


Gennady Gildenblat has got promoted to IEEE Fellow for his "contributions to modeling of metal-oxide semiconductor field effect transistors".

Yasuhisa Omura has got promoted to IEEE Fellow for the contributions made to the SOI technology, analysis and modelling.

Thomas Piotr Skotnicki also got the promotion to IEEE Fellow for contributing to the development of MOS models.



Congratulations to all of them!

Physicists from Mainz University develop a quantum interface between light and atoms

Ultra-thin glass fiber enables the controlled coupling of light and matter / publication in Physical Review Letters:

E. Vetsch, D. Reitz, G. Sagué, R. Schmidt, S. T. Dawkins, and A. Rauschenbeutel
Optical interface created by laser-cooled atoms trapped in the evanescent field surround-ing an optical nanofiber
Physical Review Letters, May 21, 2010
DOI: 10.1103/PhysRevLett.104.203603

2010 IEDM CALL FOR PAPERS

Submission Deadline is June 25, 2010!

The IEEE International Electron Devices Meeting is the Annual Technical Meeting of the Electron Devices Society.  This year it will be held at the Hilton San Francisco Union Square, San Francisco, CA USA December 6-8, 2010.

Increased participation in the areas of energy harvesting, power devices, biomedical devices and circuit-technology interaction is desired.

Information about IEDM can be found at: http://www.ieee-iedm.org

Social Networking: 
Twitter: http://twitter.com/ieee_iedm
 
Facebook:
http://www.facebook.com/search/?q=IEDM&init=quick#/pages/IEDM/131119756449?ref=search&sid=6112806.762392748..1



MEETING HIGHLIGHTS 
 * Three plenary presentations by prominent experts. 
 * Invited papers on all aspects of advanced devices and technologies. 
 * An Emerging Technology session. 
 * Panel discussion.
 * Presentation of IEEE/EDS awards. 
 * IEDM Luncheon presentation will be held on Tuesday, December 7.
 * Two short courses will be held on Sunday December 5.

Abstract Submission
 * Web-based submission of abstracts (http://www.ieee-iedm.org)
 * Deadline for submissions is June 25, 2010 

For further information on submissions, go to http://www.ieee-iedm.org and click on call for papers.  Download the pdf of the call for papers with more detailed information.

Questions/Comments, contact the IEDM Conference office at:
phyllism@widerkehr.com or 301-527-0900 ext. 2

Training Course on Compact Modeling: Final Programme

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

I want to remark that ON JUNE 30 AND JULY 1 THERE ARE NO SOCCER WORLD CUP MATCHES.

So, participants do not have to worry to miss soccer matches during the duration of the Training Course!


The final programme, with the timetable, is already available:

	Day 1: June 30, 2010 (Wednesday)
8:15		Training Courses Opening Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
8:30		Statistical variability and corresponding compact model strategies Asen Asenov (University of Glasgow)
9:45		Electrical characterization of SOI and Multi-Gate MOSFETs Sorin Cristoloveanu (MINATEC and LETI, France)
11:00		Coffee Break
11:30		Transport modeling Tibor Grasser (TU-Wien, Austria)
12:45		Analytical 2D and 3D electrostatic modeling Tor A Fjeldly (UniK, Norway)
14:15		Lunch
15:15		Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs Kiyoo Itoh (Hitachi, Japan)
16:30		GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization Wladek Grabinski
20:30		Gala Dinner
		Day 2: July 1, 2010 (Thursday)
8:30		Analytical small-signal modeling Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
9:45		DC Parameter Extraction Antonio Cerdeira (Cinvestav, Mexico)
11:00		Coffee Break
11:30		Compact, High Frequency Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET Ilcho Angelov (Chalmers University, Sweden)
12:45		Noise modeling Jamal Deen (McMaster University, Canada)
14:15		Lunch
15:15		Electro-thermal and reliability modeling Renaud Gillon (On Semiconductor, Belgium)
16:30		Leakage power modeling for the reduction of power consumption in CMOS ICs Massimo Poncino (Politecnico di Torino, Italia)
17:45		Training Courses Closing

And nice weather is usual in Tarragona at the end of June/beginning of July. Participants who spend a few more days in Tarragona can enjoy the nice beaches around, or doing sightseeing in the Tarragona area, Barcelona (only 100 Km far from Tarragona) and other places in Catalonia.

Tarragona is well connected to Barcelona by rail and highway. There are direct buses from Barcelona Airport. Besides, there are direct flights to Reus Airport (less than 15 Km far from Tarragona) from many European cities by Ryanair.

STM confirms 20nm by end of 2012

The chief technology officer at STMicroelectronics, Jean-Marc Chery, today confirmed at the Field Trip conference in London that its first 20nm process will be going into production at its French fab by Q4 2012. [more]

Intel's timbers could be shivered. In Q1 2010 alone ST had revenue of $2,323 million USD and it was the #1 EMEA semiconductor company in 2009.

Toshiba Invention Brings Quantum Computing Closer

Quantum computers are likely to be used initially to solve problems that are otherwise virtually intractable, such as modeling new molecules in pharmaceuticals. The Toshiba team, working with the University of Cambridge's Cavendish Laboratory, described their invention in a paper in the journal Nature.

Technorati Tags: quantum computers

Fastest Integrated Circuit Doubles the Previous Record, Getting Close to One Terahertz

The 670 GHz compact circuit layout (right), alongside a detail of Northrop Grumman's 30-nanometer Indium Phosphide T-gate (left). Northrop Grumman [more]

NHK Improves Resolution of Organic TFT-driven OLED Panel

NHK Science & Technology Research Laboratories (STRL) exhibited a flexible OLED panel driven by organic TFTs at OpenHouse 2010, which took place from May 27 to 30, 2010, in Tokyo [more]

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010

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To post to this group, send email to  mos-ak@googlegroups.com.
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C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop:  http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies

On-line abstract submission is open with the deadline on July 15, 2010.

Further details and updates: http://www.mos-ak.org/seville/

==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
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IEEE papers in May 2010

Why the Universal Mobility Is Not

Cristoloveanu, S.  Rodriguez, N.  Gamiz, F. 
Digital Object Identifier : 10.1109/TED.2010.2046109

AbstractPlus | Full Text: PDF (717KB)

Examples taken from ultrathin silicon-on-insulator (SOI) transistors tend to contradict the universality of mobility-field dependence. We revisit the meaning of the effective field concept and its implications on the universal mobility curve (UMC). Poisson–Schroedinger simulations point out the inappropriateness of the standard definitions of effective field when dealing with SOI or double-gate devices. Different carrier distributions can lead to the same value of the effective fie... Read More »

Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation

Akturk, A.  Holloway, M.  Potbhare, S.  Gundlach, D.  Li, B.  Goldsman, N.  Peckerar, M.  Cheung, K. P. 
Digital Object Identifier : 10.1109/TED.2010.2046458

AbstractPlus | Full Text: PDF (1193KB)

We have developed compact and physics-based distributed numerical models for cryogenic bulk MOSFET operation down to 20 K to advance simulation and first-pass design of device and circuit operation at low temperatures. To achieve this, we measured and simulated temperature-dependent current–voltage characteristics of 0.16- and 0.18-$muhbox{m}$ bulk MOSFETs. Our measurements indicate that these MOSFETs supply approxim... Read More »

Compact Modeling of Experimental n- and p-Channel FinFETs

Song, J.  Yuan, Y.  Yu, B.  Xiong, W.  Taur, Y. 
Digital Object Identifier : 10.1109/TED.2010.2047067

AbstractPlus | Full Text: PDF (339KB)

The analytic potential model for symmetric double-gate MOSFETs is verified and calibrated with experimental n- and p-channel FinFET data over a wide range of gate lengths and bias regions. Quantum mechanical effects are incorporated in the model to reproduce the measured $C$– $V$ characteristics. The long-channel mobility consists of both a phonon scat... Read More »

Compact Modeling of a Magnetic Tunnel Junction—Part I: Dynamic Magnetization Model

Kammerer, J.-B.  Madec, M.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047070

AbstractPlus | Full Text: PDF (410KB)

The potential application range of spintronic devices is wide. However, few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: the first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part, a... Read More »

Compact Modeling of a Magnetic Tunnel Junction—Part II: Tunneling Current Model

Madec, M.  Kammerer, J.-B.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047071

AbstractPlus | Full Text: PDF (498KB)

The potential application range of spintronic devices is wide. However, a few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: The first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part,... Read More »

Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design

Kashyap, A. S.  Mantooth, H. A.  Vo, T. A.  Mojarradi, M. 
Digital Object Identifier : 10.1109/TED.2010.2046073

AbstractPlus | Full Text: PDF (1337KB)

The cryogenic characterization (93 K/$- hbox{180} ^{circ}hbox{C}$ to 300 K/27 $^{circ}hbox{C}$) and compact modeling of a high-voltage (HV) laterally diffused MOS (LDMOS) transistor that exhibits carrier freeze-out are presented in this paper. Unlike low-voltage MOS devices, it was observed that HVMOS structures experience freeze-out effects at much higher t... Read More »

Variability Analysis of TiN Metal-Gate FinFETs

Endo, K.  O'uchi, S.  Ishikawa, Y.  Liu, Y.  Matsukawa, T.  Sakamoto, K.  Tsukada, J.  Yamauchi, H.  Masahara, M. 
Digital Object Identifier : 10.1109/LED.2010.2047091

AbstractPlus | Full Text: PDF (116KB)

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the $V_{rm th}$ in the FinFET occurs and the standard deviations of the $V_{rm th}$ of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the $V_{rm th}$ var... Read More »

Transistor mismatch in 32 nm high-k metal-gate process

 

Extraction Technique of Trap Densities in Thin Films and at Insulator Interfaces of Thin-Film Transistors

Kimura, M. 
Digital Object Identifier : 10.1109/LED.2010.2045221

AbstractPlus | Full Text: PDF (192KB)

We have developed an extraction technique of trap densities in thin films and at insulator interfaces of thin-film transistors (TFTs). These trap densities can be extracted and separated from capacitance–voltage and current–voltage characteristics by numerically calculating $Q = CV$ , Poisson equation, carrier density equations, and Gauss' law. The outstanding advantages are intuitive understandability and a s... Read More »

Some papers (May 2010) I've found interesting...

Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors

5457978abstract

Bronckers, S.;   Van der Plas, G.;   Vandersteen, G.;   Rolain, Y.;  
Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium 

This paper appears in: Instrumentation and Measurement, IEEE Transactions on
Issue Date: June 2010
Volume: 59 Issue:6
On page(s): 1727 - 1733
ISSN: 0018-9456
Digital Object Identifier: 10.1109/TIM.2009.2024370 
Date of Publication: 03 May 2010
Date of Current Version: 10 May 2010

Substrate noise issues are a showstopper for the smooth integration of analog and digital circuitries on the same die. For the designer, it is not known how substrate noise couples into the transistors of the analog circuitry. This paper reveals the dominant coupling mechanisms with simulations and the corresponding measurements in a 0.13-$muhbox{m}$ triple-well common-source complementary metal–oxide–semiconductor (CMOS) transistor integrated on a lightly doped substrate. Substrate noise couples in either the ground or the bulk of the transistor. It is demonstrated that the importance of the coupling mechanisms depends on the resistance of the ground interconnect. For the technology node used, measurements show that substrate noise isolation is optimal for a ground resistance of 0.8 $Omega$.

Thermal shot noise in top-gated single carbon nanotube field effect transistors

5464988abstract

Chaste, J.;   Pallecchi, E.;   Morfin, P.;   Feve, G.;   Kontos, T.;   Berroir, J.-M.;   Hakonen, P.;   Placais, B.;  
Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P. et M. Curie, Université D. Diderot, 24, rue Lhomond, 75231 Paris Cedex 05, France 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 192103 - 192103-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3425889 
Date of Current Version: 13 May 2010

The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of one-dimensional nanotransistor. In particular the prediction of a large transconductance correction to the Johnson–Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of

13 μe/

√  Hz

in the 0.2–0.8 GHz band. 

Dielectric constants of atomically thin silicon channels with double gate

Kageshima, Hiroyuki;   Fujiwara, Akira;  
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193102 - 193102-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427364 
Date of Current Version: 13 May 2010

Dielectric constants of Si (111) nanofilms with the double gate are studied in the full inversion regime by using the first-principles calculation. The calculations show that the dielectric constants are significantly smaller than that of the bulk. Further, the dielectric constants depend on the conduction type as well as on the film thickness. They also oscillate with a 2-bilayer-thickness for the p-channel case as the film thickness decreases. The suppressed dielectric constants are found in the channel center as well as in the channel surface. These findings open the way to artificial control of the dielectric constant in semiconductor nanostructures.

 

Charge carrier densities in chemically doped organic semiconductors verified by two independent techniques

Lehnhardt, M.;   Hamwi, S.;   Hoping, M.;   Reinker, J.;   Riedl, T.;   Kowalsky, W.;  
Institute for High-Frequency Technology, Technical University of Braunschweig, Schleinitzstr. 22, D-38106 Braunschweig, Germany 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193301 - 193301-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427416 
Date of Current Version: 13 May 2010

The charge carrier density of the p-type doped organic semiconductor 2,7-bis(9-carbazolyl)-9,9-spirobifluorene is determined for varied doping concentrations. As p-type dopant molybdenum trioxide is used. We determine the carrier density by measuring the polaron induced optical absorption and by a capacitance-voltage analysis. We show that both results are in excellent agreement. An almost linear dependence of the charge carrier density on the doping concentration is observed. Carrier densities on the order of 10¹⁸ cm^-3 at a dopant concentration of 1 mol % can be achieved. Overall, a low doping efficiency on the order of 2%–4.5% is evidenced.

The effect of traps on the performance of graphene field-effect transistors

Zhu, J.;   Jhaveri, R.;   Woo, J. C. S.;  
Department of Electrical Engineering, University of California–Los Angeles, Los Angeles, California 90095-1594, USA 

This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193503 - 193503-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3428785 
Date of Current Version: 13 May 2010

This paper studies the performance degradation of graphene field-effect transistors due to the presence of traps. The mobile charge modulation by gate voltage is degraded because of immobile trapped charges. As a result the current is reduced and the on/off ratio is decreased. Extracted mobility using transconductance method is shown to be underestimated considerably due to the effect of traps.

 

Training Course on Compact Modeling: Registration Open

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona, Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

The lectures and topics of their lectures will be the following:


1. Tibor Grasser (TU-Wien, Austria) - Transport modeling

2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling

3. Jamal Deen (McMaster University, Canada) - Noise modeling

4. Benjamin Iñiguez (URV, Spain) - Analytical small-signal modeling

5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling

6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling

7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs

8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies

9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"

10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"

11. Antonio Cerdeira (Cinvestav, Mexico) - "DC Parameter Extraction"

12. Massimo Poncino (Politecnico di Torino, Italia) - "Leakage power modeling for the reduction of power consumption in CMOS ICs"

The final programme, with the timetable, is already available!

May 7, 1952: The Integrated Circuit …

1952: British radar engineer Geoffrey Dummer introduces the concept of the integrated circuit at a tech conference in the United States. The world is about to change. Read more... by www.wired.com

Organic Transistor Could Outshine OLEDs

”The light-emitting transistor is a remarkably versatile device architecture,” says Alan Heeger, a physics professor at the University of California, Santa Barbara. Heeger’s lab developed an OLET inverter circuit earlier, but its quantum efficiency was much lower. He called the 5 percent external quantum efficiency ”remarkable,” because it suggests that nearly 100 percent of the carriers in the emissive layer are emitting photons. ”If that is indeed true,” Heeger says, ”they have made an important step forward.”

more at IEEE Spectrum

3rd International Workshop on Copact TFT Modeling for Circuit Simulation: Deadline Extended

The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.

Deadline for abstract submission has been extended:

- Deadline for abstract submission: May 19, 2010
- Notification of acceptance: May 26, 2010
- Camera-ready version: Jun 18, 2010

The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.

Topics:
A partial list of the areas of interest includes:

- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels

Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat



This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

EPFL MicroNano Fabrication Annual Review Meeting

The Networking Event organized by the EPFL Center of MicroNanoTechnology (CMi)

Date: Tuesday May 18th, 2010
Time: 09h30 - 17h00
Place: EPFL Lausanne, Salle Polyvalente, Centre Est, CE 1 515

Program :

• 10 invited speakers
• 163 posters

The presented topics include:

• Biomedical Applications (Microfluidics, Cellular-Manipulation, Microelectrode Arrays, Molecules Detection, BioMicroNanoSystems, ...)
• Optics (Nanophotonics, Optomechanics, Optofluidics, MOEMS, ...)
• Micro and Nanoelectronics (Nanowires, High-Q Resonators, RF MEMS and Switches, 3D integration, CMOS, ...)
• Nanostructure Physics (III/V Devices, Nanotubes, Nanowires, Nanomechanics, ...)
• Material Sciences (Graphene, Polymers, Piezoelectric Ceramics, Photovoltaic Materials, Micro Fuel Cells, ...)
• MEMS, NEMS (Motors, Tweezers, Sensors and Actuators, Micro and Nanomechanics, ...)
• Micro and Nanofabrication Technologies (Self-Assembly, EBEAM Lithography, Dry Etching, Thin Films, Photolithography, FIB, CMP, ...)
• Packaging and Assembly

Registration is required by sending an email to: claudia.dagostino@epfl.ch

Compact Modeling: Principles, Techniques and Applications

Gildenblat, Gennady (Ed.)
1st Edition., 2010, 545 p., Hardcover
ISBN: 978-90-481-8613-6
Erscheinungstermin: Juli 2010

[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville: 1st announcement

MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville
*** 1st announcement ***

Date: September 17, 2010
Venue: Barceló Hotel Renacimiento

Co-Located With:
* 40th European Solid-State Device Research Conference (ESSDERC):
http://www.essderc2010.org
* 36th European Solid-State Circuits Conference (ESSCIRC) :
http://www.esscirc2010.org
* CMC Meeting (Q3 Event in Madrid): http://www.geia.org/index.asp?bid=597

More MOS-AK/GSA information and updates: http://www.mos-ak.org/seville/

Extended MOS-AK/GSA Committee:
===========================
http://www.mos-ak.org/committee.html
===========================
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster

MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil

MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Sebastian Schmidt, XFab
Co-Chair: Prof. Benjamin Iniguez, URV

MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
===========================

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Thoughts on Directions for Silicon Technology Development as we Approach the End of CMOS Scaling

Speaker: Dr. Tak H. Ning, IBM and IEEE Fellow, and co-author of the Taur & Ning textbook now in its second edition.
Date: TUESDAY, May 11, 2010; Time: 6:00 PM - Pizza, 6:15 PM – Lecture; Cost: Free
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051
Web link: http://www.ewh.ieee.org/r6/scv/eds/
Contact: Sandeep Bahl

POWER/HVMOS Devices Compact Modeling

POWER/HVMOS Devices Compact Modeling

W. Grabinski and T. Gneiting, (Eds.)
1st Edition., 2010, V, 300 p., Hardcover
ISBN: 978-90-481-3045-0

Content Level » Research

Keywords » HV EKV, HV HiSIM,MM20, compact modeling - LDMOS, VDMOS, quasi-saturation, self heating - power, high voltage semiconductor devices

TABLE OF CONTENTS
CHAPTER 1: Numerical Power/HV Device Simulations; Oliver Triebl and Tibor Grasser.

CHAPTER 2: HiSIM-HV: A scalable, surface-potential-based compact model for symmetric and asymmetric high-voltage MOSFETs; Hans J. Mattausch, Norio Sadachika, M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch.

CHAPTER 3: MM20 HVMOS Model: a surface-potential based LDMOS model for circuit simulation; Annemarie Aarts and Alireza Tajic.

CHAPTER 4: Practical HV DMOS modeling using HVEKV; Yogesh Singh Chauhan, Francois Krummenacher and Adrian Mihai Ionescu.

CHAPTER 5: Power Devices; Andrzej Napieralski, Malgorzata Napieralska and Lukasz Starzak.

CHAPTER 6: Distributed modeling approach applied to the IGBT; Patrick Austin and Jean-Louis Sanchez.

CHAPTER 7: Web Based Modeling Tools; Andrzej Napieralski, Lukasz Starzak, Bartlomiej Swiercz and Mariusz Zubert.