Monday, June 21, 2010

[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement

"Frontiers of the Compact Modeling for Advanced Analog/RF

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010

Tentative list of the invited speakers (alphabetic order):
* Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
* Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
* Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
* Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
* David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
* Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
* Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
* Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design

Further details and updates:
* Wroclaw: June 24-26
* Tarragona: June.31-July.1
* Seville: Sept. 17
* California: Dec'2010

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