Tuesday, 11 May 2010

Training Course on Compact Modeling: Registration Open

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona, Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

The lectures and topics of their lectures will be the following:

1. Tibor Grasser (TU-Wien, Austria) - Transport modeling

2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling

3. Jamal Deen (McMaster University, Canada) - Noise modeling

4. Benjamin IƱiguez (URV, Spain) - Analytical small-signal modeling

5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling

6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling

7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs

8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies

9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"

10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"

11. Antonio Cerdeira (Cinvestav, Mexico) - "DC Parameter Extraction"

12. Massimo Poncino (Politecnico di Torino, Italia) - "Leakage power modeling for the reduction of power consumption in CMOS ICs"

The final programme, with the timetable, is already available!

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