Jul 28, 2010
MEMUNITY Workshop "Reliability, Testing, and Characterization of Micro Systems"
Jul 27, 2010
SPICE and FastSPICE, Podcast from DAC
- Pierluigi Daglio – STMicroelectronics, Agrate, Italy
- Aaron Barker – Oracle, Broomfield, CO
- Jin-Qin Lu – Atheros Communications, Inc., Santa Clara, CA
[source]
Jul 19, 2010
IBM INDIA: Job Opportunities
Job Opportunities
For more details visit website : www.ibm.com
Send resume to anibandy@in.ibm.com
Jun 30, 2010
Job offers in LinkedIn
Senior Research & Development Engineer
Group: Silicon Engineering Group
Location: Hyderabad, India
Contact @ akshat.kumar@synopsys.com
- PhD in a relevant field.
- Exp. with semiconductor back-end/ interconnect simulation tools focusing on one or, more of electrical, thermal, mechanical, and reliability analysis, numerical methods for solving partial differential equations (finite element and/or finite volume method), mesh generation.
- ~3 to 5 years of experience as a developer on large Finite Element Analysis simulators in either a commercial, or industrial/research lab setting. Prior experience with Synopsys TCAD tools is strongly preferred.
-Software development experience in C++ and preferably Tcl/Tk.
-Good communication skills and the ability to work within a team are essential.
Jun 28, 2010
some reading for summertime
Current bistability and carrier transport mechanisms of organic bistable devices based on hybrid Ag nanoparticle-polymethyl methacrylate polymer nanocomposites
Abstract: We study backscattering phenomena during conduction for graphene nanoribbons of μm lengths, from single vacancy scatterers up to finite defect concentrations. Using ab initio calibrated Hamiltonian models we highlight the importance of confinement and geometry on the shaping of the local density of states around the defects that can lead to important alterations on the transport process, giving rise to impuritylike conduction gaps in the conductance distribution. Within a statistical analysis of finite defect concentration we show that conductance degradation can become very important.
Solid-State Electronics
The spatial origin of current noise in semiconductor devices in the framework of semiclassical transport
C.E. Kormana, B.A. Noaman
Abstract: A new model to semiconductor device electronic noise is presented in the framework of semiclassical transport theory. The salient feature of this model is that it connects the current noise characteristics directly to the physics of scattering of the semiclassical transport theory and makes no additional assumption regarding the nature of noise. Employing this approach, this work investigates the spatial origin of the current noise across two semiconductor structures. In this approach the terminal current noise is directly related to carrier scattering inside the device, which is accounted for in the Boltzmann transport equation (BTE), without the need to add Langevin noise terms to the calculations. Accordingly, it utilizes the well-established spherical harmonics expansion (SHE) technique to solve the BTE, and it combines analytical and numerical methods, in contrast with the Monte Carlo (MC) approach that employs ensemble averages of randomly generated events. The model leads to the solution of a time-dependent transient solution of the BTE with special initial and Ohmic boundary conditions that is solved in the frequency domain to directly compute the terminal current noise spectral density. It is also shown that with this approach the Nyquist theorem under thermal equilibrium conditions is recovered.
Jun 23, 2010
The Ten Commandments for Effective Standards
Language: English
ISBN-10: 1617300020
ISBN-13: 978-1617300028
Karen Bartleson has three decades' experience in the computer chip industry. She is known for her work in the area of standards for electronic design automation, and is also one of the pioneers into social media in her industry, including Twitter. She is the author of "The Standards Game," a blog focused on the standards arena. Karen holds a BSEE from California Polytechnic State University, San Luis Obispo, California, and was the recipient of the Marie R. Pistilli Women in Design Automation Achievement Award in 2002. Her Twitter handle is @karenbartleson. --This text refers to the Paperback edition.
Jun 21, 2010
MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
---
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"
The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php
Tentative list of the invited speakers (alphabetic order):
* Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
* Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
* Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
* Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
* David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
* Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
* Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
* Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design
Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1 http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17 http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010 // 2nd announcement
"Frontiers of the Compact Modeling for Advanced Analog/RF
Applications"
The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010
http://mos-ak.org/seville/abstracts.php
Tentative list of the invited speakers (alphabetic order):
* Raphael Clerc, MINATEC: Compact modeling of nanoscale MOSFETs:
beyond the drift diffusion approximation
* Gilles Depeyrot, Dolphin Integration: Verilog-A Compact Model
Standardization
* Tibor Grasser, TU Wien: Recent Developments in Device
Reliability Modeling
* Benjamin Iniguez, URV: Advances in Multigate MOSFET Modeling
* David Jimenez, UAB: Analytic surface potential and drain current
model for negative capacitance FETs
* Bernabé Linares-Barranco, NMC: The EKV/ACM compact models for
mismatch modeling down to 90nm and for new emergent non-CMOS
nanotechnology FETs
* Josef Watts, IBM: Modeling Standardization: Enabling the
worldwide design community
* Sadayuki Yoshitomi, Toshiba: Device Level RF IC Design
Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1 http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17 http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
Jun 20, 2010
SPICE update from Mentor
Read more in June 18th, 2010 post by Daniel Payne in Analog Fast SPICE, DAC 2010, Fast SPICE, SPICE circuit simulation.
Jun 17, 2010
News and Views: Nature Nanotechnology
References
- Lilienfeld, J. E. Method and apparatus for controlling electric current. US patent 1,745,175 (1925)
- Shan, Y., Ashok, S. & Fonash, S. J. Appl. Phys. Lett. 91, 093518 (2007)
- Lin, Y.-W., Marek-Sadowska, M., Maly, W., Pfitzner, A. & Kasprowicz, D. in Int. Conf. Computer Design 557–562 (IEEE, 2008)
- Soree, B. & Magnus, W. in 10th Int. Conf. Ultimate Integration of Silicon 245–248 (IEEE, 2009)
- Lee, C. W. et al. Appl. Phys. Lett. 94, 053511 (2009)
- Colinge, J. P. et al. Nature Nanotech. 5, 225–229 (2010)
- Tsutsui, K. et al. in Int. Workshop Nano CMOS 56–68 (IEEE, 2006)
- Aoyama, T. et al. in Int. Workshop Junction Technol. 110–115 (IEEE, 2009)
Op-amp Spice macro-models article from Intersil
So anyway, Spice does not necessarily lie like Bob Pease says, but I guarantee you that if you give it poor models it will give you the wrong answer. This is the big hassle with op amp models. Some of them, like the old National Semi Comlinear models (pdf) published by Mike Steffes before he left for Burr Brown and now Intersil were essentially transistor-level models. An IC designer could infer the design of the part from them. Mike told me that he knew that, but it was just so important to give an accurate model that he felt he had to release those great models. If someone wanted to copy the circuits, well, they had a lot more work to do-anyone can de-cap an op amp and reverse engineer it in a day. That still does not give you the process or the testing regime or the design secrets and tricks.
That is why this Intersil article is so important. Anything that helps you make good models is important in a world where kid engineers trust a computer rather than a breadboard. The article give some history of op amp models and that will tip you off as to what you can expect from a simulation. If the model you use does not model for 1/f noise, and most vendor models do not, you cannot get a meaningful simulation of low-frequency noise performance of the circuit. If the model does include flat-band noise and you are designing and ac-coupled video circuit, well that is fine for your needs. I have yet to see a Spice op-amp model that accurately tells you what happens if you bang the output into the rails and saturate the transistors. I will ask Mike Steffes if his old Comlinear models would do that, and leave a comment.
Jun 15, 2010
Modeling The Bipolar Transistor (Book)
By Ian Getreu
The book describes the bipolar transistor model and parameter measurement techniques for the SPICE circuit simulator. Originally published by Tektronix in 1974, this is a slightly modified revision republished in 2009 by the original author.
Jun 11, 2010
IEEE Awards 2010
Takayasu Sakurai, has got the 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, for pioneering contributions to the design and modeling of high-speed and low-power CMOS logic circuits.
Note that this is not compact modeling, but his alpha power law model has had a big impact!
Gennady Gildenblat has got promoted to IEEE Fellow for his "contributions to modeling of metal-oxide semiconductor field effect transistors".
Yasuhisa Omura has got promoted to IEEE Fellow for the contributions made to the SOI technology, analysis and modelling.
Thomas Piotr Skotnicki also got the promotion to IEEE Fellow for contributing to the development of MOS models.
Congratulations to all of them!
Jun 8, 2010
Physicists from Mainz University develop a quantum interface between light and atoms
Ultra-thin glass fiber enables the controlled coupling of light and matter / publication in Physical Review Letters:
E. Vetsch, D. Reitz, G. Sagué, R. Schmidt, S. T. Dawkins, and A. Rauschenbeutel
Optical interface created by laser-cooled atoms trapped in the evanescent field surround-ing an optical nanofiber
Physical Review Letters, May 21, 2010
DOI: 10.1103/PhysRevLett.104.203603
Jun 7, 2010
2010 IEDM CALL FOR PAPERS
Submission Deadline is June 25, 2010! The IEEE International Electron Devices Meeting is the Annual Technical Meeting of the Electron Devices Society. This year it will be held at the Hilton San Francisco Union Square, San Francisco, CA USA December 6-8, 2010. Increased participation in the areas of energy harvesting, power devices, biomedical devices and circuit-technology interaction is desired. Information about IEDM can be found at: http://www.ieee-iedm.org Social Networking: Twitter: http://twitter.com/ieee_iedm Facebook: http://www.facebook.com/search/?q=IEDM&init=quick#/pages/IEDM/131119756449?ref=search&sid=6112806.762392748..1 MEETING HIGHLIGHTS * Three plenary presentations by prominent experts. * Invited papers on all aspects of advanced devices and technologies. * An Emerging Technology session. * Panel discussion. * Presentation of IEEE/EDS awards. * IEDM Luncheon presentation will be held on Tuesday, December 7. * Two short courses will be held on Sunday December 5. Abstract Submission * Web-based submission of abstracts (http://www.ieee-iedm.org) * Deadline for submissions is June 25, 2010 For further information on submissions, go to http://www.ieee-iedm.org and click on call for papers. Download the pdf of the call for papers with more detailed information. Questions/Comments, contact the IEDM Conference office at: phyllism@widerkehr.com or 301-527-0900 ext. 2
Jun 3, 2010
Training Course on Compact Modeling: Final Programme
The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.
REGISTRATION IS OPEN
It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.
I want to remark that ON JUNE 30 AND JULY 1 THERE ARE NO SOCCER WORLD CUP MATCHES.
So, participants do not have to worry to miss soccer matches during the duration of the Training Course!
The final programme, with the timetable, is already available:
Day 1: June 30, 2010 (Wednesday) | ||
8:15 | Training Courses Opening Benjamin Iniguez (Universitat Rovira i Virgili, Spain) | |
8:30 | Statistical variability and corresponding compact model strategies Asen Asenov (University of Glasgow) | |
9:45 | Electrical characterization of SOI and Multi-Gate MOSFETs Sorin Cristoloveanu (MINATEC and LETI, France) | |
11:00 | Coffee Break | |
11:30 | Transport modeling Tibor Grasser (TU-Wien, Austria) | |
12:45 | Analytical 2D and 3D electrostatic modeling Tor A Fjeldly (UniK, Norway) | |
14:15 | Lunch | |
15:15 | Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs Kiyoo Itoh (Hitachi, Japan) | |
16:30 | GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization Wladek Grabinski | |
20:30 | Gala Dinner | |
| ||
| Day 2: July 1, 2010 (Thursday) | |
8:30 | Analytical small-signal modeling Benjamin Iniguez (Universitat Rovira i Virgili, Spain) | |
9:45 | DC Parameter Extraction Antonio Cerdeira (Cinvestav, Mexico) | |
11:00 | Coffee Break | |
11:30 | Compact, High Frequency Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET Ilcho Angelov (Chalmers University, Sweden) | |
12:45 | Noise modeling Jamal Deen (McMaster University, Canada) | |
14:15 | Lunch | |
15:15 | Electro-thermal and reliability modeling Renaud Gillon (On Semiconductor, Belgium) | |
16:30 | Leakage power modeling for the reduction of power consumption in CMOS ICs Massimo Poncino (Politecnico di Torino, Italia) | |
17:45 | Training Courses Closing |
And nice weather is usual in Tarragona at the end of June/beginning of July. Participants who spend a few more days in Tarragona can enjoy the nice beaches around, or doing sightseeing in the Tarragona area, Barcelona (only 100 Km far from Tarragona) and other places in Catalonia.
Tarragona is well connected to Barcelona by rail and highway. There are direct buses from Barcelona Airport. Besides, there are direct flights to Reus Airport (less than 15 Km far from Tarragona) from many European cities by Ryanair.
STM confirms 20nm by end of 2012
Intel's timbers could be shivered. In Q1 2010 alone ST had revenue of $2,323 million USD and it was the #1 EMEA semiconductor company in 2009.
Jun 2, 2010
Toshiba Invention Brings Quantum Computing Closer
Jun 1, 2010
Fastest Integrated Circuit Doubles the Previous Record, Getting Close to One Terahertz
The 670 GHz compact circuit layout (right), alongside a detail of Northrop Grumman's 30-nanometer Indium Phosphide T-gate (left). Northrop Grumman [more]
May 30, 2010
NHK Improves Resolution of Organic TFT-driven OLED Panel
May 27, 2010
[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"
The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies
On-line abstract submission is open with the deadline on July 15, 2010.
Further details and updates: http://www.mos-ak.org/seville/
==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1 http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17 http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
May 26, 2010
IEEE papers in May 2010
Why the Universal Mobility Is Not
Cristoloveanu, S. Rodriguez, N. Gamiz, F.Digital Object Identifier : 10.1109/TED.2010.2046109
Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation
Akturk, A. Holloway, M. Potbhare, S. Gundlach, D. Li, B. Goldsman, N. Peckerar, M. Cheung, K. P.Digital Object Identifier : 10.1109/TED.2010.2046458
Compact Modeling of Experimental n- and p-Channel FinFETs
Song, J. Yuan, Y. Yu, B. Xiong, W. Taur, Y.Digital Object Identifier : 10.1109/TED.2010.2047067
Compact Modeling of a Magnetic Tunnel Junction—Part I: Dynamic Magnetization Model
Kammerer, J.-B. Madec, M. Hébrard, L.Digital Object Identifier : 10.1109/TED.2010.2047070
Compact Modeling of a Magnetic Tunnel Junction—Part II: Tunneling Current Model
Madec, M. Kammerer, J.-B. Hébrard, L.Digital Object Identifier : 10.1109/TED.2010.2047071
Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design
Kashyap, A. S. Mantooth, H. A. Vo, T. A. Mojarradi, M.Digital Object Identifier : 10.1109/TED.2010.2046073
Variability Analysis of TiN Metal-Gate FinFETs
Endo, K. O'uchi, S. Ishikawa, Y. Liu, Y. Matsukawa, T. Sakamoto, K. Tsukada, J. Yamauchi, H. Masahara, M.Digital Object Identifier : 10.1109/LED.2010.2047091
Transistor mismatch in 32 nm high-k metal-gate process
Extraction Technique of Trap Densities in Thin Films and at Insulator Interfaces of Thin-Film Transistors
Kimura, M.Digital Object Identifier : 10.1109/LED.2010.2045221
May 18, 2010
Some papers (May 2010) I've found interesting...
Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors
- 5457978abstract
Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium
Issue Date: June 2010
Volume: 59 Issue:6
On page(s): 1727 - 1733
ISSN: 0018-9456
Digital Object Identifier: 10.1109/TIM.2009.2024370
Date of Publication: 03 May 2010
Date of Current Version: 10 May 2010
Thermal shot noise in top-gated single carbon nanotube field effect transistors
- 5464988abstract
Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P. et M. Curie, Université D. Diderot, 24, rue Lhomond, 75231 Paris Cedex 05, France
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 192103 - 192103-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3425889
Date of Current Version: 13 May 2010
The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of one-dimensional nanotransistor. In particular the prediction of a large transconductance correction to the Johnson–Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of
13 μe/ |
|
Dielectric constants of atomically thin silicon channels with double gate
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193102 - 193102-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427364
Date of Current Version: 13 May 2010
Charge carrier densities in chemically doped organic semiconductors verified by two independent techniques
Institute for High-Frequency Technology, Technical University of Braunschweig, Schleinitzstr. 22, D-38106 Braunschweig, Germany
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193301 - 193301-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427416
Date of Current Version: 13 May 2010
The charge carrier density of the
The effect of traps on the performance of graphene field-effect transistors
Department of Electrical Engineering, University of California–Los Angeles, Los Angeles, California 90095-1594, USA
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193503 - 193503-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3428785
Date of Current Version: 13 May 2010
This paper studies the performance degradation of graphene field-effect transistors due to the presence of traps. The mobile charge modulation by gate voltage is degraded because of immobile trapped charges. As a result the current is reduced and the on/off ratio is decreased. Extracted mobility using transconductance method is shown to be underestimated considerably due to the effect of traps.
May 11, 2010
Training Course on Compact Modeling: Registration Open
The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.
The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.
REGISTRATION IS OPEN
It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.
The lectures and topics of their lectures will be the following:
1. Tibor Grasser (TU-Wien, Austria) - Transport modeling
2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling
3. Jamal Deen (McMaster University, Canada) - Noise modeling
4. Benjamin Iñiguez (URV, Spain) - Analytical small-signal modeling
5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling
6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling
7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs
8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies
9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"
10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"
11. Antonio Cerdeira (Cinvestav, Mexico) - "DC Parameter Extraction"
12. Massimo Poncino (Politecnico di Torino, Italia) - "Leakage power modeling for the reduction of power consumption in CMOS ICs"
The final programme, with the timetable, is already available!
May 8, 2010
May 7, 1952: The Integrated Circuit …
1952: British radar engineer Geoffrey Dummer introduces the concept of the integrated circuit at a tech conference in the United States. The world is about to change. Read more... by www.wired.com
Organic Transistor Could Outshine OLEDs
May 7, 2010
3rd International Workshop on Copact TFT Modeling for Circuit Simulation: Deadline Extended
Deadline for abstract submission has been extended:
- Deadline for abstract submission: May 19, 2010
- Notification of acceptance: May 26, 2010
- Camera-ready version: Jun 18, 2010
The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.
Topics:
A partial list of the areas of interest includes:
- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat
This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
May 5, 2010
EPFL MicroNano Fabrication Annual Review Meeting
Date: Tuesday May 18th, 2010
Time: 09h30 - 17h00
Place: EPFL Lausanne, Salle Polyvalente, Centre Est, CE 1 515
Program :
The presented topics include:
- Biomedical Applications (Microfluidics, Cellular-Manipulation, Microelectrode Arrays, Molecules Detection, BioMicroNanoSystems, ...)
- Optics (Nanophotonics, Optomechanics, Optofluidics, MOEMS, ...)
- Micro and Nanoelectronics (Nanowires, High-Q Resonators, RF MEMS and Switches, 3D integration, CMOS, ...)
- Nanostructure Physics (III/V Devices, Nanotubes, Nanowires, Nanomechanics, ...)
- Material Sciences (Graphene, Polymers, Piezoelectric Ceramics, Photovoltaic Materials, Micro Fuel Cells, ...)
- MEMS, NEMS (Motors, Tweezers, Sensors and Actuators, Micro and Nanomechanics, ...)
- Micro and Nanofabrication Technologies (Self-Assembly, EBEAM Lithography, Dry Etching, Thin Films, Photolithography, FIB, CMP, ...)
- Packaging and Assembly
May 4, 2010
Compact Modeling: Principles, Techniques and Applications
1st Edition., 2010, 545 p., Hardcover
ISBN: 978-90-481-8613-6
Erscheinungstermin: Juli 2010
May 3, 2010
[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville: 1st announcement
*** 1st announcement ***
Date: September 17, 2010
Venue: Barceló Hotel Renacimiento
Co-Located With:
* 40th European Solid-State Device Research Conference (ESSDERC):
http://www.essderc2010.org
* 36th European Solid-State Circuits Conference (ESSCIRC) :
http://www.esscirc2010.org
* CMC Meeting (Q3 Event in Madrid): http://www.geia.org/index.asp?bid=597
More MOS-AK/GSA information and updates: http://www.mos-ak.org/seville/
Extended MOS-AK/GSA Committee:
===========================
http://www.mos-ak.org/committee.html
===========================
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Sebastian Schmidt, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
===========================
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
May 2, 2010
Thoughts on Directions for Silicon Technology Development as we Approach the End of CMOS Scaling
Date: TUESDAY, May 11, 2010; Time: 6:00 PM - Pizza, 6:15 PM – Lecture; Cost: Free
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051
Web link: http://www.ewh.ieee.org/r6/scv/eds/
Contact: Sandeep Bahl
Apr 29, 2010
POWER/HVMOS Devices Compact Modeling
1st Edition., 2010, V, 300 p., Hardcover
ISBN: 978-90-481-3045-0
Keywords » HV EKV, HV HiSIM,MM20, compact modeling - LDMOS, VDMOS, quasi-saturation, self heating - power, high voltage semiconductor devices
CHAPTER 1: Numerical Power/HV Device Simulations; Oliver Triebl and Tibor Grasser.
CHAPTER 2: HiSIM-HV: A scalable, surface-potential-based compact model for symmetric and asymmetric high-voltage MOSFETs; Hans J. Mattausch, Norio Sadachika, M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch.
CHAPTER 3: MM20 HVMOS Model: a surface-potential based LDMOS model for circuit simulation; Annemarie Aarts and Alireza Tajic.
CHAPTER 4: Practical HV DMOS modeling using HVEKV; Yogesh Singh Chauhan, Francois Krummenacher and Adrian Mihai Ionescu.
CHAPTER 5: Power Devices; Andrzej Napieralski, Malgorzata Napieralska and Lukasz Starzak.
CHAPTER 6: Distributed modeling approach applied to the IGBT; Patrick Austin and Jean-Louis Sanchez.
CHAPTER 7: Web Based Modeling Tools; Andrzej Napieralski, Lukasz Starzak, Bartlomiej Swiercz and Mariusz Zubert.