May 5, 2021

Speed Up SPICE with a GPU

Speed Up SPICE with a GPU

Circuit designers know that SPICE circuit simulators use a large matrix to simultaneously solve for currents and voltages, taking small enough time steps to ensure convergence and simulation stability. The trouble is that using a general purpose CPU to make these matrix calculations is quite time consuming, meaning that an engineer can wait hours or days to see any simulation results. Since necessity is the mother of all invention, some clever EDA engineers have looked to speed up SPICE circuit simulations by using GPUs.

1.) Nascentric

2.) TinySPICE

3.)with CUSPICE

4.) CUDA Circuit Simulator

5.)Empyrean

6.) Synopsys
The need to simulate IC designs in a reasonable amount of time at the transistor level has become a real bottleneck for standard cell, memory design and AMS IP design. Designing with FinFET and small geometry nodes only increases the amount of process corners that need to be simulated for a robust design, so speeding up SPICE simulations is quite welcomed. It looks like using a GPU to speed things up is gaining traction in both the commercial and academic segments, and Daniel Payne loves to hear how Synopsys does against the underdog Empyrean [read more...]




IEEE Milestone - ST Multiple Silicon Technologies



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May 05, 2021 at 10:39AM
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#Top10 (less 5) Capacity Leaders



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May 05, 2021 at 10:53AM
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We Could Really Have a #Wireless #Power Grid That Runs on #5G



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May 4, 2021

[paper] Random Telegraph Noise in Metal‐Oxide Memristors



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May 04, 2021 at 02:37PM
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[Si2 CMC] to Standardize SPICE Model for SiC MOSFET

May 03, 2021 // By Peter Clarke [eenewsanalog.com

The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.

Silicon-carbide offers higher efficiency and faster operation than silicon and has been adopted for several power applications including photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution. A CMC working group will oversee the model development with Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys set to participate.

"I'd encourage companies with a stake in silicon-carbide devices to join this effort and help guide selection of the model which best represents their intended use," 
advised Peter Lee, chair of the CMC.

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability [Read more...]

May 3, 2021

[paper] FET Library for VLSI

Taehak Kim1, Jaehoon Jeong2, Seungmin Woo2, Jeonggyu Yang1, Hyunwoo Kim2 Ahyeon Nam2, Changdong Lee2, Jinmin Seo2, Minji Kim2, Siwon Ryu2, Yoonju Oh2, and Taigon Song1,2  
NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes 
IEEE ISCAS, 2021, pp. 1-5, DOI 10.1109/ISCAS51556.2021.9401055.

1School of Electronics Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
2School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea


Abstract: Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology. 

Fig: Projected 3nm NSFET library development flow. Upper side of each step shows the names of required tools. Each colored-boxes correspond to the steps required for specific tasks: The blue boxes - device development, the orange boxes - digital design, and the green boxes - back end design, respectively.

Acknowledgements: This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2020M3H2A1078045). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2019R1G1A109470212).