Fwd: Announcement of Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates (Sept 14-19, 2020) jointly organized by Science Foundation and MHRD-IIC-DDUC Chapter, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (Under the aegis of DBT Star College Program)

On behalf of Science Foundation and MHRD-IIC-DDUC Chapter, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (Under the aegis of DBT Star College Program), I would like to invite you to kindly register for the Online Lecture Workshop On Frontiers in Science & Engineering - Opportunities for Graduates scheduled for September 14-19, 2020.

The workshop is likely to be supported by the Science Academies and will be organized using CISCO WEBEX/Microsoft Teams.

All Interested Science and Engineering Students and Faculty Members are requested to kindly register on 

or before August 25, 2020 via link appended below

https://docs.google.com/forms/d/e/1FAIpQLSfFA3Yp7quiJN8fZTJrCR8jkyE4XA8Ddr0hdMi5r5IEiTctVg/viewform  

There is NO REGISTRATION FEES. I request you to kindly motivate your students and colleagues to register for the same.

Organizing Committee

• Professor Anurag Sharma, FNA, FNASc, FASc, FNAE, JC Bose National Fellow (SERB), Department of Physics, IIT Delhi (Convener-Workshop)
• Professor Ajoy Ghatak, NASI Meghnad Saha Distinguished Professor, Chairperson-NASI Delhi Chapter.
• Dr. Manoj Saxena, Coordinator-Workshop, Deen Dayal Upadhyaya College, University of Delhi, New Delhi (msaxena@ddu.du.ac.in)
• Committee Members of Science Foundation, MHRD-IIC-DDUC Chapter and DBT Star College Program of  Deen Dayal Upadhyaya College, University of Delhi.

with regards

Dr. Manoj Saxena | डॉ मनोज  सक्सेना 

Associate Professor | सह - आचार्य

Department of Electronics | इलेक्ट्रॉनिक्स विभाग

Deen Dayal Upadhyaya College | दीन दयाल उपाध्याय कॉलेज

University of Delhi | दिल्ली विश्वविद्यालय

Dwarka Sector-3, New Delhi-110078 | द्वारका क्षेत्र -३, नई दिल्ली -११००७८

India | भारत

Official Homepage: https://dducollegedu.ac.in/ViewProfile.aspx?fId=saxenamanoj77@gmail.com

ORCID Webpage : http://orcid.org/0000-0002-9368-4194

Scopus Webpage : http://www.scopus.com/authid/detail.url?authorId=35480023200

ResearcherID-Thomson Reuters : http://www.researcherid.com/rid/K-3863-2015 

Publons Profile: https://publons.com/researcher/1341187/manoj-saxena

Please do not print this email unless it is absolutely necessary. Spread environmental awareness. 

Fwd: IEEE-EDS Santa Clara Valley/San Francisco Chapter August Seminar (Webex only)

Please note that this seminar is now WEBEX participation only! 

Memory Errors in Production Systems – Insights from the Field

Speaker: Dr. Sudhanva Gurumurthi, Principal Member of Technical Staff, AMD

Friday, August 28, 2020 at 12PM – 1PM PDT

Register Here

Abstract: Memory reliability is important for the correct operation of computing systems. While technology scaling has paved the way for improvements in the capacity and energy-efficiency of memory, the reliability aspects of such scaling must be well characterized and addressed in the design of computer hardware. AMD has collected and analyzed memory reliability data from several production systems running in data centers. This data spans several generations of DRAM technologies, as well as SRAM. This talk will first explain how bit-cell reliability can impact on the design and use of computing hardware and highlight the importance of studying memory faults from commercial hardware in the field. The talk will then present memory reliability data and insights from AMD's field studies and discuss their implications from the viewpoint architecting resilient systems.

Speaker Bio: Sudhanva Gurumurthi is a Principal Member of the Technical Staff at AMD, where he leads advanced development in Reliability, Availability, and Serviceability (RAS). He used to be an Associate Professor with tenure in the Computer Science Department at the University of Virginia. Sudhanva is a recipient of the NSF CAREER Award, a Google Focused Research Award, two Google Faculty Research Awards, and other NSF and industry awards. He is a Senior Member of the IEEE and the ACM. 

 

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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[paper] SPICE model of p‐Si TFET

Sola Woo Juhee Jeon Sangsig Kim 

A SPICE model of p‐channel silicon tunneling field‐effect transistors for logic applications

IJNM: 06 August 2020; DOI: 10.1002/jnm.2793

¹Department of Electrical Engineering,Korea University, Seoul, South Korea

Abstract: In this study, we propose a SPICE model of p-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricated p-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters, c-TFET NAND gates, and c-TFET NOR gates using our TFET model. Our simulation shows that a c-TFET inverter can be operated at VDD as low as 0.3?V and that c-TFET logic gates based on our model can operate ~1000 times higher frequency than conventional TFET logic gates.

FIG: 2D structure of p-TFET for our simulation 

and its simulated/measured transfer characteristics at VDS=-1.0V

Acknowledgements: This research was partly supported by the MOTIE (Ministry of Trade, Industry & Energy) (10067791) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device, the Brain Korea 21 Plus Project in 2020, and Samsung electronics.

You don't need a computer science degree to work with #opensource software https://t.co/cpAlOk7V7U https://t.co/u3bNQ295sK

You don't need a computer science degree to work with #opensource software https://t.co/cpAlOk7V7U pic.twitter.com/u3bNQ295sK

— Wladek Grabinski (@wladek60) August 6, 2020

from Twitter https://twitter.com/wladek60

August 06, 2020 at 05:14PM
via IFTTT

Call for Chapters

Title: Sub-Micron Semiconductor Devices: Design and Applications

Introduction: To follow Moore’s law, semiconductor devices are scaled-down without compromising the performance. Semiconductor devices are supposed to be reduced in dimensions and work at lower operating biases but the problem arises during the manufacturing of the devices. Thus, it is a dire necessity to opt for a solution that can help in continuing the path of performance improvement. Steady performance enhancement using optimization techniques can support the time required for advancements in fabrication technologies. This publication confines the novel semiconductor devices, issues with conventional devices, optimization techniques and solutions for the performance enhancement. Even with the presence of a vast amount of data regarding semiconductor devices, it is hard for a researcher to go through most of the recent advancements altogether and understand them in a clear way. The motive behind the book is to comprehensibly present the material related to the recent advancements in the field of semiconductor devices that can allow the reader to interpret the possible concepts behind the content. The study of novel semiconductor devices may help in unraveling the mystery behind the problems that are required to tackle during the fabrication of molecular devices.

Topics: [Not limited to the given topics but relevant topics will be considered as well]

• Basic of Scaled-Down Devices
• (Nano-FET, TFET, LED, Solar Cell, TFT, HEMT, Diodes, RTDs, Photodiode, Quantum-Dots, Spin-FET, etc.)
• Comparative Study of Novel Semiconductor Devices
• Inclusion of Quantum Effects in Nano-Devices
• (Short Channel Effects, Fermi-Level-Pinning, Quantum Confinement, Discrete DOS, etc.)
• Device Modelling and Physics
• (Analytical, Compact, NEGF, Quantum, Verilog, Spice, etc.)
• Novel Materials for Devices
• (Graphene, Silicene, TMDCs, Organic, Perovskite, 2D Materials, TCO, Photo-dielectric, etc.)
• Characterization and Fabrication
• (Spectroscopic, Microscopic, MBE, CVD, Spin-Coating, Defects, etc.)
• Optimization Techniques
• (Negative Capacitance, Feedback, Gate-on-Source, Dopingless, 2DEG, Schottky Contact, etc.)
• Testing of Semiconductor Devices
• Applications
• (Biosensor, Radiation Sensor, Light Sensor, Analog/Digital Circuit Applications, MEMS, etc.)
• Issues and Solutions of Novel devices
• Future Device Technology

Important Dates (Updated):

Chapter Proposal Submission: 10 September 2020 Notification of Acceptance: 15 September 2020 Full Chapter Submission: 25 October 2020

Review Result Returned: 30 October 2020 Final Acceptance: 10 November 2020 Publication of Book: January-February 2021

Submission:

Kindly submit the chapter proposal [Tittle, Abstract (500-1000 words), Possible Content, Author details] before the due date via E-mail at call.chapters.crc@gmail.com. Any kind of query regarding the chapter or abstract submission, formatting and corrections can be submitted to query.chapters.crc@gmail.com

Editors:

Ashish Raman¹, Deep Shekhar² and Naveen Kumar³

Electronics and Communication Engineering Department, Dr. B. R. Ambedkar National Institute of Technology Jalandhar, [Grand Trunk Road, Barnala - Amritsar Bypass Rd, Jalandhar, India 144011] 

Official E-mail IDs: ¹ ramana@nitj.ac.in, ² deeps.ec.18@nitj.ac.in, ³ naveenk.ec.16@nitj.ac.in

[chapter] Design of FET Biosensors

Khuraijam Nelson Singh¹ and Pranab Kishore Dutta¹

Chapter 8: Analytical Design of FET-Based Biosensors

in Advanced VLSI Design and Testability Issues; Eds: Suman Lata et all.

CRC Press, 19 Aug 2020; 360 pages

¹NERIST, Arunachal Pradesh, India

Abstract: Research on biosensors has seized the interested researchers over the past few decades due to their various advantages and applications. They are used in the discovery of drugs, monitoring of diseases, agriculture, food quality control, industrial wastage monitoring, military, etc. The sensing analyte is the main element that differentiates a biosensor from the other physical/chemical sensors. In general, the biosensor is a device that is used to detect an analyte using a biosensitive receptor. Its main components are as follows:

• Analytes: The substance that is intended to be detected, such as glucose in a glucose sensor, ammonia in ammonia sensor, and so on.
• Bioreceptors: The bioreceptors are biosensitive elements used to detect target analytelbiomolecule. They are sensitive to the analytes of interest. Some examples of bioreceptors are antigen, DNA, enzyme, and so on.
• Transducers: The elements that are used to convert energy from one form to another are called transducers. In a biosensor, the interaction of analytes and bioreceptors produces changes in the form of heat, gas, light, ions, or electrons. These changes are then converted into a quantif‌iable form by the transducer. Usually, the output of the transducer is in the form of electrical or optical signals, and the generated signal is proportional to the interaction between the analyte and the biosensor.

FIG: Schematic diagram of ion-sensitive f‌ield-effect transistor (ISFET)

[paper] GCC Method for Determining MOSFET VTH

Matthias Bucher¹, Nikolaos Makris¹, Loukas Chevas¹

Generalized Constant Current Method for Determining MOSFET Threshold Voltage

arXiv:2008.00576v1 (2 Aug 202) 

has been submitted to the IEEE for possible publication

¹ School of Electrical and Computer Engineering, Technical University of Crete

Abstract: A novel method for extracting threshold voltage (VTH) and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect related parameters. The method is applicable over a wide range of current throughout weak and moderate inversion and to some extent in strong inversion. This method is particularly useful when applied for MOSFETs presenting edge conduction effect (subthreshold hump) in CMOS processes using Shallow Trench Isolation (STI).

Fig:  Application of the GCC method in presence of edge conduction phenomenon in STI MOSFETs. A constant current is applied to determine pinchoff voltage for the center transistor in moderate inversion at IC=2. To characterize the edge transistor, imposing a current criterion IC=1E−4 corresponds to ICe≈0.02. Pinchoff voltage (VP) and slope factor n characteristics illustrate the determination of parameters for center and edge transistors.

Acknowledgment: This work was partly supported under Project INNOVATION-EL-Crete

(MIS 5002772).