[mos-ak] [Final Program] 16th International MOS-AK Workshop Silicon Valley, Dec. 13, 2023

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

16th International MOS-AK Workshop

Silicon Valley, December 13, 2023

Together with Keysight Technologies team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 16th International MOS-AK Workshop in Silicon Valley.

Scheduled 16th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The content will be beneficial for anyone who needs to learn what is really behind the FOSS CAD/EDA IC simulation in modern device models in Open Access PDKs.

The MOS-AK workshop program is available online:

<https://www.mos-ak.org/silicon_valley_2023/>

Venue:

Keysight Technologies

5301 Stevens Creek Boulevard

Santa Clara, CA 95051

Online Free Registration; 

any related enquiries can be sent to registration@mos-ak.org

-- W.Grabinski on the behalf of International MOS-AK Committee

WG291023

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[paper] Noise modeling for cryogenic applications

Giovani Britton^1,2, Salvador Mir², Estelle Lauga-Larroze², Benjamin Dormieu¹, Quentin Berlingard^3,4, Mickael Casse³ and Philippe Galy¹

Noise modeling using look-up tables and DC measurements for cryogenic applications.

VLSI-SoC 2023 - 31st IFIP/IEEE International Conference on Very Large Scale Integration,

Oct 2023, Sharjah, United Arab Emirates.

DOI: 10.1109/VLSI-SoC57769.2023.10321896
hal-04305746

1STMicroelectronics, Crolles, France

2Univ. Grenoble Alpes, CNRS, Grenoble-INP, TIMA

3Univ. Grenoble Alpes, CEA, LETI

4Univ. Grenoble Alpes, CNRS, Grenoble-INP, IMEP-LAHC

Abstract : There is today a lack of mature transistor-level compact models for the simulation of integrated circuits at cryogenic temperatures. This is particularly the case for the simulation of the noise behavior which is critical for most applications. In this paper, we aim at an efficient prediction of the white noise behavior of basic amplifying stages working at RF frequencies and cryogenic temperatures. For this, we propose the use of DC measurements that are incorporated in a LookUp Table (LUT) and fed to a mathematical noise model. We illustrate the approach for the case of a transistor in common source configuration. The results of circuit simulation of the noise parameters in the standard temperature range are very close to the estimation of the same parameters using the LUT with just DC measurements. The approach can be readily extended to the analysis of circuits with multiple components. Next, the LUT approach is used for estimating the noise parameters at cryogenic conditions, considering DC measurements that have been carried out at these temperatures. The paper illustrates the feasibility of carrying out a cryogenic design using a LUT-based approach while accurate compact models are not yet available.

Fig : Measurement data and EKV or ACM generated parameters are added

to the LUT generated by the interface between EDA tools

Acknowledgments : This work was supported by the French program Conventions Industrielles de Formation par la Recherche (CIFRE) and Labex MINOS of French program ANR-10-LABX-55-01.

[PhD] ULTRARAM™ at Lancaster University

Lancaster University, Physics Department has three open PhD Projects, Programmes & Scholarships

• Scaling ULTRARAM™ on FindAPhD.com
  The PhD project will further advance the development of ULTRARAM™ memory. ULTRARAM™ is an ultra-efficient, multi-award-winning memory technology that combines the non-volatility of flash with the speed and endurance of dynamic random access (DRAM).
• Vertical-cavity surface-emitting lasers for below-screen consumer (and other) applications at Lancaster University on FindAPhD.com
  The PhD project will further develop a patented approach to implementing vertical-cavity surface-emitting lasers (VCSELs) operating at telecoms wavelengths
• Novel compound-semiconductor logic for computing applications on FindAPhD.com
  The PhD project will further develop a patent-pending alternative approach to digital logic that abandons the CMOS paradigm underpinning computing

Supervisor: Prof. M. Hayne

Application deadline: 29 February 2024 // Competition Funded PhD Project (UK Students Only)

Chips JU Launch Event

 

https://www.chipsjulaunchevent.eu/

Agenda Day 1: Embracing the voice of stakeholders

12:00 - 14:30	Registration
13:00 - 15:30	Networking lunch and exhibition "Walk of Fame" opening and guided tour
15:30 - 15:40	Welcome and opening, Jari Kinaret, Executive Director of the Chips JU
15.40 - 16:00	Keynote speech, Thierry Breton, European Commissioner for Internal Market
16:00 - 16:20	Intro speeches "EU strategic autonomy and economic security"
	Nikolai Setzer, CEO, Continental AG
	Jaime Martorell, Special Commissioner for Microelectronics and Semiconductors, Spain
16:20 - 17:20	1st Panel discussion with a moderator
	Thomas Skordas, DDG, CNECT, European Commission
	Pierre Barnabé, CEO, Soitec
	Roger Dassen, CFO, ASML
	Luc Van den hove, President and CEO, imec
	Frédérique Le Grévès, President & CEO, STMicroelectronics France
	Cinzia Silvestri, CEO, Bi/ond
	Alain Jarre, Chairman and CEO, RECIF Technologies
17:20 - 17:40	Coffee break
17:40 - 18:00	Intro speeches "Maintaining and boosting European technology leadership"
	Jochen Hanebeck, CEO, Infineon Technologies AG
	Jo Brouns, Flemish Minister for Economy, Innovation, Work, Social Economy, and Agriculture
18:00 - 19:00	2nd Panel discussion with a moderator
	Signe Ratso, Deputy Director-General, DG RTD, European Commission
	European Semiconductor Board Member (name tbc)
	Stefan Finkbeiner, CEO, Bosch Sensortec GmbH
	Maurice Geraets, Executive Director, NXP Semiconductors Netherlands B.V.
	Sébastien Dauvé, CEO, CEA-Leti
	Eva Maydell, Member of the European Parliament
	Joost van Kuijk, CEO/CMO, Adimec
19:00 - 19:05	Closing remarks by the moderator
19:15	Shuttle bus to the social event venue
20:00 - 22:30	Social event and walking dinner “Art & History Museum of Belgium”

Day 2 Part 1: Presentation of the Initiative

08:00 - 09:00	Registration & welcome coffee
09:00 - 09:10	Intro speech by Lucilla Sioli, Director DG CNECT.A, European Commission
09:10 - 09:40	New advanced pilot lines: Yves Gigase, Head of Programmes, Anton Chichkov, Programme Officer, Chips JU
09:40 - 09:55	Network of competence centre: Yves Gigase, Head of Programmes, and Anton Chichkov, Programme Officer, Chips JU
09:55 - 10:10
	Cuting-edge quantum chips: Gustav Kalbe, acting Director DG CNECT C, and
	Christian Trefzger, Policy Officer, DG CNECT, European Commission
10:10 - 10:25	Chips Fund: EC, EIB, EIC joint presentation
10:25 - 10:55	Q&A
10:55 - 11:25	Coffee break, networking and exhibition
11:25 - 12:15	Interactive session on Advanced design platform: Marco Ceccarelli and Matihew Xuereb, Policy Officers, DG CNECT, European Commission
12:15 - 13:40	Networking lunch.

Day 2 Part 2: Chips JU R&I Programme

13:40 - 13:50	Intro speech by Jean-Luc di Paola-Galloni, Chair of the Chips JU Private Members Board
13:50 - 14:50	3rd Panel discussion with a moderator
	Lucilla Sioli, Director, DG CNECT.A, European Commission
	Michael Paulweber, Director Global ITS Research & Technology, AVL List
	Régis Hamelin, CTO, Blumorpho
	Francis Balestra, Director of Research CNRS
	Ferdinand Bell, Head of Public Collaborative Programs, NXP Semiconductors, Germany GmbH
	Christoph Kutier, Vice-Chair, Fraunhofer Microelectronics Group/FMD
	Bert de Jonge, CEO, VERUM
14:50 - 15:20	ECS SRIA 2024 – What is new? Patrick Cogez, Technical Director, AENEAS IA
15:20 - 15:50	Upcoming Chips JU calls and focus topics
	Yves Gigase, Head of Programmes, and Anton Chichkov, Programme Officer, Chips JU
15:50 - 16:00	Closing remarks Jari Kinaret, Executive Director of the Chips JU
16:00 - 17:30	Coffee break, networking and exhibition

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions