[paper] p-Type Doped Silicene-based

Mu Wen Chuan, Munawar Agus Riyadi, Afiq Hamzah, Nurul Ezaila Alias, Suhana Mohamed Sultan, Cheng Siong Lim, Michael Loong Peng Tan

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

PLoS ONE 17(3): e0264483.: March 3, 2022

DOI: 10.1371/journal.pone.0264483

   
Universiti Teknologi Malaysia, Skudai, Johor, Malaysia
Diponegoro University, Semarang, Indonesia

Abstract: Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Fig: Schematic diagrams of AlSi3 FET: (a) the structure and 

(b) the ToB nanotransistor circuit model. 

Acknowledgements: 1.) Michael Tan Loong Peng - Ministry of Higher Education (MOHE) of Malaysia through the Fundamental Research Grant Scheme(FRGS/1/2021/ STG07/ UTM/02/3); The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. 2.) Munawar Agus Riyadi - World Class Research Universitas Diponegoro (WCRU) 2021 Grant no. 118-16/UN7.6.1/PP/2021; The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

[paper] Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs

Kerim Yilmaz, Benjamín Iñíguez, François Lime, and Alexander Kloes

Cryogenic Temperature and Doping Analysis of Source-to-Drain Tunneling Current in Ultrashort-Channel Nanosheet MOSFETs

IEEE TED, Vol. 69, No. 3, March 2022

DOI: 10.1109/TED.2022.3145339   

NanoP, THM Giessen (D)
DEEEA, Universitat Rovira i Virgili, Tarragona (SP)

Abstract:This work analyzes the impact of doping concentration on the temperature-dependent subthreshold current and swing saturation due to direct source-to-drain tunneling (DSDT) in short-channel silicon nanosheet (SiNS) metal–oxide–semiconductor field-effect transistors (MOSFETs). Furthermore, their influence on the drain-induced barrier lowering (DIBL) effect is investigated. Special attention is paid to the importance of the Fermi level and the average tunneling energy, whose energetic positions and distance from each other in the band diagram has a significant role in the temperature-dependent saturation behavior of the subthreshold current and swing, as well as the value of DIBL. Furthermore, we model and present with device simulation the existence of two merging subthreshold swings (Ssth) and DIBL effects with increasing gate bias at cryogenic temperatures. The merging is achieved by the superposition of the DSDT and thermionic emission (TE) current, which originate from their own dominated and visibly separated gate-bias regions.

FIG: First subband energy of the conduction band together with a color plot showing the electron energy dependent normalized tunneling and TE current densities at an operating

temperature T0=300K with S/D doping of Ns/d=1E20cm^−3

 

Let’s get back to the business of building microchips in America

[https://t.co/UiC0Uc61OM] Gina Raimondo: “Let’s get back to the business of building microchips in America” #semi https://t.co/GuMK2hWVKj

— Wladek Grabinski (@wladek60) Mar 7, 2022

---

from Twitter https://twitter.com/wladek60

March 07, 2022 at 09:07AM
via IFTTT

[mos-ak] Re: MOS-AK/Guangzhou // Q1 2022 MOS-AK Panel: Compact Model Verilog-A standardization and implementation

On Fri, Feb 25, 2022 at 9:18 AM zhang@xmodtech.cn <zhang@xmodtech.cn> wrote:

Dear Wladek,

we will hold MOS-AK guangzhou event in August, 11-12th.  two days.  10th. August can be used for one day training. 

Now, we come to the invited talk, have you good candidate for this year event?

thanks for your email and update on MOS-AK/Guangzhou workshop planning.

We have organized MOS-AK panel dedicated to the compact model Verilog-A implementation/validation (see below). This is a "hot" R&D topic in our domain. I would suggest to invite the researchers working on the FOSS TCAD/EDA tools for compact modeling support. There is interesting work done by GnuCap, ngspspice, Qucs, Xyce teams and many others. Let's also explore that topics with your local partners eg: Cogenda and local host in Guangzhou 

I will be gald if you can introduce myself to your organization team in Guangzhou, too.

-- thanks and have a nice weekend -- wladek;

 

 Many thanks.

regards,

min

On Wed, Mar 2, 2022 at 4:53 PM Wladek Grabinski <wladek@grabinski.ch> wrote:

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

Q1 2022 MOS-AK Panel

Online Publications

The Extended MOS-AK Committee, has organized a very first MOS-AK Panel to discuss the FOSS EDA tools for the compact/SPICE modeling and its Verilog-A standardization and implementation. The Q1 2022 MOS-AK Panel was organized as the virtual/online event on Feb.25, 2022, with practive participation of leading FOSS EDA developers representing GnuCap, ngspice, Qucs, Xyce teams.

Online Publications:

There are MOS-AK technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization; see submitted slide presentations online at corresponding link:

https://www.mos-ak.org/panel_Q1_2022/

The MOS-AK Panelists have also contributed to FOSS EDA/Verilog-A SWOT Analysis, with selected points listed in the table below. The FOSS EDA community has a number of challenges to address, in particular, securing financial support for FOSS EDA tools developments, especially for those outside of the corporate/academic environment, is of primary concern.

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe thru the Next 2022 Year, including:

• Spring MOS-AK Workshop (online) Mar/Apr 2020
• 4th MOS-AK/LAEDC Workshop, Cancun (MX) July 2022
  
• 6th Sino MOS-AK Workshop (CN), Aug. 2022
• 20th MOS-AK/ESSDERC/ESSCIRC, Milano Sept.19, 2022
• 3rd MOS-AK/India Conference, Hyderabad (IN) Postponed 2022
• 15th US MOS-AK Workshop, Silicon Valley (US) Dec. 2022
• in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski on the behalf of International MOS-AK Committee

WG02032022

Table: FOSS EDA/Verilog-A SWOT Analysis

Strengths	Weaknesses
High number of potential users both in terms of EDA companies/vendors and designers High number of potential contributors once a tool as been established as "gold standard"	At least a bit financial support will be needed in the long-run
Opportunities	Challenges
A "gold standard" Verilog-A compiler, i.e. sth. Like gcc, g++ or gfortran is currently not available for Verilog-A Improve the usefulness of open-source tools dramatically Enabler for research around the world  Further improving the Verilog-A standard and enabling new modeling technologies in the long-term	Securing financial support for FOSS developments, especially for those outside of the corporate/academic environment Teamwork, between projects

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[paper] Charge Trapping/Detrapping in Scaled MOSFETs

Ruben Asanovski, Pierpaolo Palestri*, and Luca Selmi

Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs

IEEE TED, Vol. 69, No. 3, March 2022 1313

DOI: 10.1109/TED.2022.3147158

  

 Università degli Studi di Modena e Reggio Emilia, Modena, Italy

*Università degli Studi di Udine, Udine, Italy

Abstract: Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

Fig: (a) FinFET with the single trap location highlighted. (b) Drain current noise comparison between TCAD simulations at VGS = 0.7 V, VDS = 25 mV and single trap located as in (a).