[Overview] Radiation Damage Effects in Microelectronic Devices

Yanru Ren1, Min Zhu¹, Dongyu Xu^1,2, Minghui Liu¹, Xuehui Dai¹, Shengao Wang1,
and Longxian Li¹

Overview on Radiation Damage Effects and Protection Techniques in Microelectronic Devices

Review Article; Open Access; Volume 2024; Article ID 3616902; 

DOI 10.1155/2024/3616902

1 Naval University of Engineering, Wuhan 430033, China
2 PLA Unit 91049, Sanya 572000, China

Abstract: With the rapid advancement of information technology, microelectronic devices have found widespread applications in critical sectors such as nuclear power plants, aerospace equipment, and satellites. However, these devices are frequently exposed to diverse radiation environments, presenting significant challenges in mitigating radiation-induced damage. Hence, this review aims to delve into the intricate damage mechanisms of microelectronic devices within various radiation environments and highlight the latest advancements in radiation-hardening techniques. The ultimate goal is to bolster the reliability and stability of these devices under extreme conditions. The review initiates by outlining the spectrum of radiation environments that microelectronic devices may confront, encompassing space radiation, nuclear explosion radiation, laboratory radiation, and process radiation. It also delineates the potential damage types that these environments can inflict upon microelectronic devices. Furthermore, the review elaborates on the underlying mechanisms through which different radiation environments impact the performance of microelectronic devices, which includes a detailed analysis of the characteristics and fundamental mechanisms of damage when microelectronic devices are subjected to total ionizing dose effects and single-event effects. In addition, the review delves into the promising application prospects of several key radiation-hardening techniques for enhancing the radiation tolerance of microelectronic devices.

FIG: The equivalent circuit of the EKV-RAD macromodel

Acknowledgments: The study was funded by Key Construction Projects of Academic Disciplines (430618) Construction Projects of Key Universities and Key Disciplines (430183).

[paper] Characteristics and ultra-high total ionizing dose response

Termo, Gennaro, Giulio Borghello, Federico Faccio, Kostas Kloukinas, Michele Caselle, Alexander Friedrich Elsenhans, Ahmet Cagri Ulusoy, Adil Koukab, and Jean-Michel Sallese

 Characteristics and ultra-high total ionizing dose response 

of 22 nm fully depleted silicon-on-insulator

Journal of Instrumentation 19, no. 03 (2024): C03039

DOI 10.1088/1748-0221/19/03/C03039

a CERN, Geneva, Switzerland

b École Polytechnique Fédérale de Lausanne, Switzerland

c Karlsruhe Institute of Technology, Germany

Abstract: The radiation response of MOS transistors in a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO2) with different back-gate bias configurations, from −8 V to 2 V. The investigation revealed that the performance is significantly affected by TID, with the radiation response being dominated by the charge trapped in the buried oxide.

Fig: Schematic of the irradiated transistors in 22 nm FDSOI 

Complementary paper:

[1] Termo, Gennaro, Giulio Borghello, Federico Faccio, Stefano Michelis, A. Koukab, and J-M. Sallese. "Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID." Journal of Instrumentation 18, no. 01 (2023): C01061.

[paper] Chip Placement with Deep Learning

Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Sungmin Bae Azade, Nazi Jiwoo, Pak Andy, Tong Kavya Srinivasa, William Hang, Emre Tuncer, Anand Babu Quoc, Le James Laudon, Richard Ho, Roger Carpenter, Jeff Dean

Chip placement with deep reinforcement learning

arXiv preprint:2004.10746 (2020)

Abstract: In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process. Unlike prior methods, our approach has the ability to learn from past experience and improve over time. In particular, as we train over a greater number of chip blocks, our method becomes better at rapidly generating optimized placements for previously unseen chip blocks. To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas. To enable our RL policy to generalize to unseen blocks, we ground representation learning in the supervised task of predicting placement quality. By designing a neural architecture that can accurately predict reward across a wide variety of netlists and their placements, we are able to generate rich feature embeddings of the input netlists. We then use this architecture as the encoder of our policy and value networks to enable transfer learning. Our objective is to minimize PPA (power, performance, and area), and we show that, in under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator netlists, whereas existing baselines require human experts in the loop and take several weeks.

Fig: Visualization of placements. On the left, zero-shot placements from the pre-trained policy and on the right, placements from the finetuned policy are shown. The zero-shot policy placements are generated at inference time on a previously unseen chip. The pre-trained policy network (with no fine-tuning) places the standard cells in the center of the canvas surrounded by macros, which is already quite close to the optimal arrangement and in line with the intuitions of physical design experts.

Acknowledgments: This project was a collaboration between Google Research and the Google Chip Implementation and Infrastructure (CI2) Team. We would like to thank Cliff Young, Ed Chi, Chip Stratakos, Sudip Roy, Amir Yazdanbakhsh, Nathan Myung-Chul Kim, Sachin Agarwal, Bin Li, Martin Abadi, Amir Salek, Samy Bengio, and David Patterson for their help and support.

[book] NANOELEKTRONIK Bauelemente der Zukunft

 

NANOELEKTRONIK

Bauelemente der Zukunft

Edition: 2., updated and expanded edition

• Alexander Klös

eISBN: 978-3-446-47900-5

Print ISBN: 978-3-446-47899-2

© 2024 Carl Hanser Verlag GmbH & Co. KG

Vorwort zur 2. Auflage

Kaum ein Gebiet der Ingenieurwissenschaften entwickelt sich so rasant wie die Nanoelektronik. Seit der Drucklegung der ersten Auflage dieses Buchs wurden neue Bauelementkonzepte entwickelt, die für die weitere Entwicklung der Großintegration sehr vielverspechend sind.

Heute bereiten die drei wirtschaftlich größten Halbleiterhersteller den Übergang zu sogenannten Nanosheet-Transistoren vor. Durch konsequente Weiterentwicklung dieses Konzepts haben 2D-Materialien in der Nanoelektronik inzwischen eine große Bedeutung erlangt und werden für neue Transistorstrukturen erforscht. Diese Entwicklungen sind jetzt in der neuen Auflage des Buchs enthalten.

Weiterhin wurden die Grundlagenkapitel zur Halbleiterphysik erweitert, um dem Anspruch des Buchs als umfassendes und alleiniges Begleitbuch für Vorlesungen auch in Masterstudiengängen gerecht zu werden. Hierbei wird insbesondere der Einführung der Bandstruktur von Halbleitern und der Berechnung von Tunnelströmen mehr Raum gewidmet. Eine Vielzahl von kleineren Änderungen und Aktualisierungen in allen sonstigen Kapiteln und eine Übersicht der empfohlenen Simulationstools auf der Plattform nanohub.org runden die neue Auflage ab.

An dieser Stelle sei darauf hingewiesen, dass aus Gründen einer einheitlichen Darstellung im Text und in den grafischen Darstellungen der Punkt als Dezimaltrennzeichen entsprechend dem englischen Sprachraum verwendet wird.

Chapter	Pages
Nanoelektronik	1–13
1 Einführung in die Nanoelektronik	15–18
2 Eigenschaften von Halbleitern	19–38
3 Teilchen und Wellen	39–64
4 Bandstruktur und Bändermodell	65–104
5 Ladungstransport in Halbleitern	105–124
6 Grundlagen der Halbleitertechnologie	125–146
7 Klassische Bauelemente der Mikroelektronik	147–222
8 Digitale CMOS-Schaltungstechnik	223–242
9 Nanostruktur-Feldeffekttransistoren	243–302
10 Alternative Nanostruktur-MOSFETs	303–334
Konstanten und Materialparameter	335–336
Simulationstools	337–344
Formelzeichen	345–350
Literatur	351–354
Index	355–362

[OSDA 2024] 4th Workshop on Open-Source Design Automation

4th Workshop on Open-Source Design Automation

OSDA 2024

at DATE Palacio De Congresos València, Spain

25 Mar 2024

Organiser: Christian Krieg, TU Wien, Austria

OSDA intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and re-usability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.

Agenda:

Christian Krieg; Post-Doctoral Researcher and Teacher at TU Wien

Welcome Session

Luca Carloni ;Professor at Columbia University

ESP: An Open-Source Platform for Collaborative Design of Heterogeneous Systems-on-Chip

Jean-Paul Chaput; Engineer at Sorbonne Université

Update on the Coriolis EDA Toolchain

Dirk Koch; Professor at Heidelberg University

FABulous: An embedded eFPGA Framework - an Update

Matthew Venn; Founder at YosysHQ, TinyTapeout

Demo Pitch: Tiny Tapeout

Claire Xenia Wolf; CTO at YosysHQ

Yosys

Frans Skarman PhD Student at Linköping University

Surfer -- An Extensible and Snappy Waveform Viewer

Poster Session

• Vojtech Mrazek
  An Open-Source Automated Design Space Exploration Framework for Approximate Accelerators in FPGAs and ASICs
• Marc Solé i Bonet, Aridane Alvarez Suarez and Leonidas Kosmidis
  The METASAT Hardware Platform v1.1: Identifying the Challenges for its RISC-V CPU and GPU Update
• Louis Ledoux and Marc Casas
  The Grafted Superset Approach: Bridging Python to Silicon with Asynchronous Compilation and Beyond
• Manfred Schlägl, Christoph Hazott and Daniel Große
  RISC-V VP++: Next Generation Open-Source Virtual Prototype
• Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó and Jonathan Balkind
  Using Supercomputers to Parallelize RTL Simulations
• Davide Cieri
  Hog (HDL on git): a tool to manage HDL code on a git repository
• Jakob Ratschenberger and Harald Pretl
  RALF: A Reinforcement Learning Assisted Automated Analog Layout Design Flow
• Ajeetha Kumari Venkatesan, Anirudh Pradyumnan Srinivasan, Deepa Palaniappan
  Adding configurability to PySlint using TOML
• Lucas Klemmer and Daniel Grosse
  WSVA: A SystemVerilog Assertion to WAL Compiler