MINIMAL

"Minimal Fab Promotion Organization" (MINIMAL) aim is to establish a completely new production method called this minimal fab and initiating a process revolution in Japan. The mission is to further expand the application fields of Minimal Fab as the only organization in the world to support the spread and development of high-mix low-volume of microdevices such as semiconductors and MEMS as innovative industrial systems. We are aiming to become an innovation platform to promote small businesses using the Minimal Fab through collaboration among various industries such as various toolmakers, materials, parts and device users [ read more...]

INUP-i2i - Idea to Innovation

INUP-i2i

Indian Nanoelectronics Users’ Programme

Idea to Innovation

Ministry of Electronics and Information Technology – MeitY, with the long-term vision of improving skilled manpower in the areas of micro and nanoelectronics had established the Indian Nanoelectronics Users’ Programme (INUP) about a decade back. The initiative enabled the researchers to travel from the country's remotest locations and implement their ideas at the state-of-art nanofabrication and characterization facilities available at Centres of Excellence established at the Indian Institute of Science Bangalore and Indian Institute of Technology Bombay. Over the years, the brand INUP has caught the imaginations of the scholars from numerous technical colleges and universities who could not afford to have such facilities to perform research. The user base grew from the first (2008-2014) to the second 2014-2019) phases of implementation. Thousands of researchers have received hands-on training at various levels in such state-of-art facilities in the multi-disciplinary areas of micro/nanoelectronics. Hundreds of them could implement their research ideas and produce scientific and technological outputs. The initiative resulted in unprecedented benefits to the budding scholars in developing cutting-edge research prototypes, which was found to be way beyond the traditional soft-teaching pathways through textbook knowledge. The initiative also helped the participants write and submit research proposals, budget the same, implement ideas at the ground level, schedule project work, submit project reports, prepare scientific manuscripts, and develop the devices.

INUP-i2i OBJECTIVES

• Enhance R&D ecosystem in the area of nanoelectronics by leveraging the Nano centres established by MeitY.
• Conduct training/workshops in the field of Nanoelectronics for wider dissemination of knowledge.
• Support the exploratory and innovative research for development of technologies in Nanoelectronics
• Mentor startups for commercialization of nanotechnologies.
• Conduct Hackathons/Grand Challenge targeting societal applications to develop Nano engineered solutions.

Hands-on training workshop are organized on the following different themes:

• Sensors and Microfluidics
• Organic Electronics
• 2D materials and devices
• Logic & Memory Devices
• Spintronics
• Compound Semiconductor Devices
• Photovoltaics
• MEMS

[read more...]

[paper] Cryogenic Devices for Quantum Technologies

Jorge Pérez-Bailón, Miguel Tarancón, Santiago Celma, and Carlos Sánchez-Azqueta

Cryogenic Measurement of CMOS Devices for Quantum Technologies

IEEE Transactions on Instrumentation and Measurement (2023)

Quantum Materials and Devices (Q-MAD) Group

Institute of Nanoscience and Materials of Aragón (INMA),

Group of Electronic Design (GDE), University of Zaragoza (SP)

Abstract: In this article we present the experimental characterization of active components of a standard 65nm CMOS technology for a temperature range from 313 to 5K, analyzing the variation of the main parameters over temperature and voltage, recovering their main parameters (threshold voltage Vth, transconductance Gm and channel conductance GDS). The measurement has been carried out wire-bonding the bare dies with the devices to a dedicated printed circuit board (PCB) that has been placed inside a dilution refrigerator. The ID-VDS curves for both NMOS and PMOS transistors shows an increase of ID in the cryogenic regime that is more relevant for high values of VGS because for lower values it is partially compensated by the variation of Vth. Also, a kink is observed in these curves for high VDS values, caused by the bulk current generated by impact ionization at the drain combined with the increased resistivity of the frozen-out substrate. The transconductance Gm reaches non-zero values for higher VGS as T decreases, and then peaks to higher values in the cryogenic regime. In turn, GDS increases for increasing T, following the behavior observed for ID. Both results are in accordance with other thermal characterizations carried out on CMOS transistors in different technologies.

Fig: Detail of the IC in the measurement setup to fit into the cryostat

Aknowlegemetns: This work was supported in part by the Spanish Ministry of Science and Innovation under Grant PID2020-114110RA-I00; and in part by the CSIC Program for the Spanish Recovery, Transformation and Resilience Plan funded by the Recovery and Resilience Facility of the European Union, established by the Regulation (EU) 2020/2094 under Grant 20219PT007

IWPSD 2023

XXII International Workshop on Physics of Semiconductor Devices

Research Park, IIT Madras, Chennai - 600036

Dec. 13-17, 2023

organised by

Indian Institute of Technology Madras

@ Research Park, IIT Madras

in association with

Society for Semiconductor Devices (SSD)

Semiconductor Society (India)

The XXII International Workshop on the Physics of Semiconductor Devices (IWPSD 2023) is being jointly organized by the Indian Institute of Technology Madras in collaboration with Society for Semiconductor Devices and Semiconductor Society (India). This series of biennial workshops, started in 1981, provides a global forum for interaction between scientists and technologists working in the area of semiconductor materials and devices.

The topics to be covered in the Workshop are, but not limited to:

• 2D Materials and Devices
• Crystal Growth and Epitaxy
• Device Modelling and Simulation
• Devices for Quantum Technology
• II - VI and Oxide Semiconductors
• III - V Semiconductors
• Memory and Logic Devices
• MEMS, NEMS and Sensors
• Organic and Flexible Electronics
• Photovoltaics
• Power Semiconductor Devices
• Optoelectronics

IWPSD 2023 Registration is open. Registration fees includes admission to all conference sessions, daily lunch and tea breaks, conference kit and dinner/banquet.

Contact: <admin.iwpsd2023@ee.iitm.ac.in>

[paper] Analog System Synthesis for Reconfigurable Computing

Afolabi Ige, Linhao Yang, Hang Yang, Jennifer Hasler, and Cong Hao

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

J. Low Power Electron. Appl. 2023, 13, 58. 

DOI: 10.3390/jlpea1304005

* Electrical and Computer Engineering (ECE), Georgia Institute of Technology (USA)

Abstract: The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.

Figure: The analog synthesis tool flow to generate a design on a large-scale Field Programmable Analog Array (FPAA) or an Application-Specific Integrated Circuit (ASIC). A single user-supplied high-level description goes through multiple lowering steps to reach the targeted output, either GDSII or a switch list. For targeting an FPAA, a design can either be specified through the GUI in XCOS (a pre-existing flow) or through the new text-based Python flow. Users construct circuits and systems using class objects provided in the Python cell library that mirror the palette browser in the XCOS library, and the description is then lowered into a Verilog syntax. The FPAA path lowers to Blif netlist, fitting into our preexisting flow compiling a switch list to target the FPAA. For targeting an ASIC, users perform similar steps to construct a system from Python objects with cells made available in the provided library. Those Python objects are then converted to a Verilog netlist before being fed to the layout synthesis modules, which handle placement and global routing. These serve as inputs to the open-source detailed router (TritonRoute) to convert the guide to a path. That path is merged with the placement file to create a final output layout file.

Funding: Partial funding for the development of this effort came from NSF (2212179).