[paper] Reconfigurable Characteristics in MoS2 Transistors

Matteo Farronato, Fabio Carletti, Niccolò Garegnani, Anupam Jana, Matteo Porzani, Saverio Ricci, Augusta Ungarelli, Christian Monzio Compagnoni, Paolo Fantini, Innocenzo Tortorelli, Agostino Pirovano, Christian Rinaldi and Daniele Ielmini

Voltage-controlled reconfigurable characteristics in MoS2 transistors 

via ion migration for reprogrammable logic.

NPJ 2D Mater Appl (2026)

DOI: 10.1038/s41699-026-00720-2

1 DEIB, Politecnico di Milano and IU.NET, Milano, Italy

2 Dipartimento di Fisica, Politecnico di Milano, Italy

3 Micron Technology Inc., Vimercate (MB), Italy

Abstract: 2D semiconductors such as MoS2 offer a promising pathway for future logic and analog transistors and memories. These materials feature scalable channel size, back-end of the line compatibility, and high mobility for relatively small channel thickness approaching few atomic monolayers. An open issue for the development of mature 2D-based digital technology is the availability of both n- and p-type transistors, as well as the ability to control the transistor type in a reconfigurable way. This work presents a novel MoS2-based transistor exhibiting reconfigurable n- or p-type characteristics, namely switching from n-type to p-type and vice versa, which is attributed to ion-assisted doping from the gate dielectric layer. Extensive characterization of the device shows repeatable switching with relatively low cycle-to-cycle (C2C) and device-to-device (D2D) variability. A reconfigurable p-n junction is demonstrated via a junction-less multi-gate MoS2-based transistor. We also demonstrate various reconfigurable logic gates, including a complementary metal-oxide-semiconductor (CMOS) inverter, a fully n-type inverter and an XNOR logic gate based on MoS2 transistors, showcasing the generality and flexibility of channel reconfiguration for logic circuit applications. These results underscore the strong potential of reconfigurable MoS2 transistors for ultra-scaled, reconfigurable logic circuits.

Fig: Logic gates with reconfigurable MoS2 transistors. (a) SEM image of a logic inverter or CMOSNOT gate with two transistors in the same MoS2 flake. (b) Schematic of the inverter with reconfigurable MoS2 transistors and logic truth table.

Acknowledgments: This article has received funding from the European Research Council (ERC) under the EuropeanUnion’s Horizon Europe Research and Innovation Programme (grant 101054098). Authors want tothank all the Polifab (the micro and nano technology infrastructure of Politecnico di Milano) staff fortheir help in the fabrication of the MoS2-based devices.

[paper] Analog System Synthesis for Reconfigurable Computing

Afolabi Ige, Linhao Yang, Hang Yang, Jennifer Hasler, and Cong Hao

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

J. Low Power Electron. Appl. 2023, 13, 58. 

DOI: 10.3390/jlpea1304005

* Electrical and Computer Engineering (ECE), Georgia Institute of Technology (USA)

Abstract: The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.

Figure: The analog synthesis tool flow to generate a design on a large-scale Field Programmable Analog Array (FPAA) or an Application-Specific Integrated Circuit (ASIC). A single user-supplied high-level description goes through multiple lowering steps to reach the targeted output, either GDSII or a switch list. For targeting an FPAA, a design can either be specified through the GUI in XCOS (a pre-existing flow) or through the new text-based Python flow. Users construct circuits and systems using class objects provided in the Python cell library that mirror the palette browser in the XCOS library, and the description is then lowered into a Verilog syntax. The FPAA path lowers to Blif netlist, fitting into our preexisting flow compiling a switch list to target the FPAA. For targeting an ASIC, users perform similar steps to construct a system from Python objects with cells made available in the provided library. Those Python objects are then converted to a Verilog netlist before being fed to the layout synthesis modules, which handle placement and global routing. These serve as inputs to the open-source detailed router (TritonRoute) to convert the guide to a path. That path is merged with the placement file to create a final output layout file.

Funding: Partial funding for the development of this effort came from NSF (2212179).

[paper] 20 Years of Reconfigurable Field-Effect Transistors

T. Mikolajick^1,2, G. Galderisi¹, M. Simon¹, S. Rai³, A. Heinzig², A. Kumar³, 

W.M. Weber⁴, J. Trommer¹

20 Years of Reconfigurable Field-Effect Transistors: From Concepts to Future Applications 

22th Conference on Insulating Films on Semiconductors 

INFOS2021

28 June-2 July 2021, Rende, Italy

1 NaMLab GmbH, Nöthnitzer Str. 64a, Dresden, Germany
2 Chair of Nanoelectronics, TU Dresden, Germany
3 Chair of Processor Design, TU Dresden, Dresden, Germany
4 Chair of Nanoelectronics, TU Wien, Vienna, Austria

Outline

• Introduction
• The Reconfigurable Field Effect Transistor
• Early Phase
• Device Outgrowth
• Functional Diversification
• Summary and Outlook