[paper] VNWFET-based technology

VNWFET-based technology: from device modelling to standard cell library

Sara Mannaa, Cedric Marchand, Damien Deleruyelle, Bastien Deveautour, 

Ian O’Connor, Alberto Bosio

2023 IEEE 23rd International Conference on Nanotechnology (NANO),

Jeju City, S.Korea, 2023, pp. 576-581

DOI: 10.1109/NANO58406.2023.10231288

Univ Lyon, ECL, INSA Lyon, CNRS, UCBL, CPE Lyon, INL, UMR5270, 69130 Ecully, France

Abstract: Vertical Nanowire Field Effect Transistors (VNWFETs) are an emerging technology with significant potential to reduce footprint and consequently interconnect capacitance, thereby achieving improved energy-efficiency and being naturally compatible with advanced 3D integration approaches. However, while initial estimations have focused on projections and estimations, no work has so far used a detailed compact model to attempt accurate transistor-level simulations for standard cell library characterization, thus enabling logic synthesis. In this paper, we propose a design flow to make the link from an existing (laboratory-scale) VNWFET technology and the associated compact model, to standard static logic cell design and characterization, and ultimately logic synthesis. To the best of our knowledge, this is the first work to prove the possibility of such a realistic design flow tailored to VNWFET technologies.

Fig: Through actual VNWFET fabrication setting up a design-technology co-optimization (DTCO) approach, the FVLLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to fine-grain hardware / software co-optimisation.

Acknowledgment: This work has been founded by FVLLMONTI European Union’s Horizon 2020 research and innovation programme under grant agreement No 101016776.

Call for Book Chapters

Nanoscale Electronic Device Applications of Carbon Nanotubes,

Graphene, Silicene and Molybdenum Disulfide

[C4P] EDTM Conference 2024, Bangalore

8th IEEE Electron Devices Technology and Manufacturing

EDTM Conference 2024

Theme: Strengthening Globalization in Semiconductors

Hilton Bangalore, India, March 3rd- 6th, 2024

https://ewh.ieee.org/conf/edtm/2024/

Call for Paper: We cordially invite you to submit ORIGINAL 3-page Camera-Ready papers to the 2024 IEEE Electron Devices Technology and Manufacturing (IEEE EDTM 2024) Conference for possible presentations. Original papers are sought on any topic within the scope of IEEE EDTM 2024. There are 14 R&D Tracks for IEEE EDTM 2024, among them:

TRACK 9. Modeling and Simulation (MS)

Advances in modeling/simulation of devices, packages and processes; Technology CAD and benchmarking; Atomistic process and device simulation; Compact models for DTCO and STCO; AI/ML-augmented modelling; Material and interconnect modeling; Models for photonic devices.

Important Dates for Authors

• Three-page camera-ready paper submission starts: August 1,2023
• Paper submission deadline: October 15, 2023 October 30, 2023 
• Notification for Acceptance: December 15, 2023

Accepted IEEE EDTM 2024 papers will be considered for competition for the Best Paper Award, Best Student Paper Awards and Best Poster Awards.

More details on paper submission can be found at the Paper Submission webpage.

[Proceedings] MNDCS 2023

Micro and Nanoelectronics Devices, Circuits and Systems

Select Proceedings of MNDCS 2023

Part of the book series: Lecture Notes in Electrical Engineering (LNEE, volume 1067) DOI: 10.1007/978-981-99-4495-8

Editors: Trupti Ranjan Lenka, Samar K. Saha, Lan Fu

This book presents select proceedings of the International Conference on Micro and Nanoelectronics Devices, Circuits and Systems (MNDCS-2023). The book includes cutting-edge research papers in the emerging fields of micro and nanoelectronics devices, circuits, and systems from experts working in these fields over the last decade. The book is a unique collection of chapters from different areas with a common theme and is immensely useful to academic researchers and practitioners in the industry who work in this field.

[paper] The Future Transistors

Wei Cao, Huiming Bu, Maud Vinet, Min Cao, Shinichi Takagi, Sungwoo Hwang, Tahir Ghani

and Kaustav Banerjee

The future transistors

Nature vol. 620, pp. 501–515 (2023)

DOI: 10.1038/s41586-023-06145-x

Abstract: The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary metal–oxide–semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

FIG: The history of transistor technology.

Acknowledgements: K.B. acknowledges support from the Army Research Office (grant W911NF1810366), the Air Force Office of Scientific Research (grant FA9550-18-1-0448), the Japan Science and Technology Agency CREST Program (grant SB180064) and the National Science Foundation (grant CCF 2132820). K.B. thanks the following individuals for their selfless support during the organization of the collaboration: T. Ernst, CEA-LETI, Grenoble, France; T. Sakurai, The University of Tokyo, Tokyo, Japan; J. Welser, IBM Almaden Research Centre, San Jose, USA. K.B. also thanks S. Oda, Tokyo Institute of Technology, Ōokayama, Japan, for useful discussions.