[papers] Biosensors for Agriculture, Environment and Food

---

J. Ajayan, P. Mohankumar, R. Mathew, L. R. Thoutam, B. K. Kaushik and D. Nirmal

"Organic Electrochemical Transistors (OECTs)

Advancements and Exciting Prospects for Future Biosensing Applications" 

in IEEE Transactions on Electron Devices, vol. 70, no. 7, pp. 3401-3412, July 2023

DOI: 10.1109/TED.2023.3271960

Abstract: Over the past few decades, the field of organic electronics has depicted proliferated growth, due to the advantageous characteristics of organic semiconductors, such as tunability through synthetic chemistry, simplicity in processing, cost-effectiveness, and low-voltage operation, to cite a few. Organic electrochemical transistors (OECTs) have recently emerged as a highly promising technology in the area of biosensing and flexible electronics. OECT-based biosensors are capable of sensing brain activities, tissues, monitoring cells, hormones, DNAs, and glucose. Sensitivity, selectivity, and detection limit are the key parameters adopted for measuring the performance of OECT-based biosensors. This article highlights the advancements and exciting prospects of OECTs for future biosensing applications, such as cell-based biosensing, chemical sensing, DNA/ribonucleic acid (RNA) sensing, glucose sensing, immune sensing, ion sensing, and pH sensing. OECT-based biosensors outperform other conventional biosensors because of their excellent biocompatibility, high transconductance, and mixed electronic–ionic conductivity. At present, OECTs are fabricated and characterized in millimeter and micrometer dimensions, and miniaturizing their dimensions to nanoscale is the key challenge for utilizing them in the field of nanobioelectronics, nanomedicine, and nanobiosensing. URL

---

Y. Wu et al., 

"A Dynamic Concentration-Dependent Analytical I,–V Model for LG-GFET Biosensor" 

in IEEE Transactions on Electron Devices, vol. 70, no. 6, pp. 3255-3262, June 2023, 

DOI: 10.1109/TED.2023.3268139.

Abstract: In the past few years, liquid-gated graphene field-effect transistors (LG-GFETs) have been widely used in biological detection due to their unique advantages. An accurate transistor model is the basis of biological detection circuit design, however, the reported GFET models are mainly focusing on solid-gated GFETs. Therefore, it is essential to conduct the research on LG-GFET model. In this article, an improved  IV  model of LG-GFET is presented based on Fregonese’s model. An improved electric double-layer capacitor model is proposed for LG-GFET. Then, the relationship among iron concentration, bias voltages, and current is studied comprehensively. Furthermore, the drain current response change with time is taken into account and the dynamic concentration-dependent model is established. To verify the accuracy of the proposed model, LG-GFET is simulated in TCAD software and fabricated to perform the measurement. The simulation results and measurement results are compared with the model results, respectively. These results show that the relative root-mean-square error (RMSE) to both simulation and measurement results is less than 5.7%. It is revealed that the proposed model can be applied to biological detection and achieve high accuracy.URL

---

Special Issue "Biosensors for Agriculture, Environment and Food"

Biosensors (ISSN 2079-6374) an Open Access Journal by MDPI

Editor-in-Chief Prof. Dr. Giovanna Marrazza 

Department of Chemistry “Ugo Schiff”, University of Florence, Italy

Food safety has become a hot issue concerned by governments, people and society. Biosensors have been playing a greater vital role in monitoring agro-products and their production process to ensure end-foods’ quality and safety, and they usually demonstrate a lot of benefits, such as being sensitive, rapid, portable, cheap and especially suitable for on-site testing. So, this topic will concern the development of biosensors and analytical methods, especially for chemicals, microorganisms, biotoxins in agriculture, environment and food samples. It is suggested that biosensors should be in line with the trend of five “S”, Sensitivity, Specificity (Selection), Speed, Simultaneously, Small (Smart), and that all detection methods should be validated using agriculture, environment or food samples. Interdisciplinary research and integrative application research related to biosensors are also encouraged, including review articles and research articles.

[mos-ak] [Final Program] 5th International MOS-AK/LAEDC Workshop, July 2, 2023, Puebla (MX)

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

5th International MOS-AK/LAEDC Workshop

July 3, 2023, Puebla (MX)

Final Workshop Program

Together with Profs Benjamin Iñiguez Nicolau, and Roberto S. Murphy Arteaga, local MOS-AK/LAEDC workshop coordinators, the LAEDC Organizers as well as all the Extended MOS-AK TPC Committee, would like to invite you to the 4th International MOS-AK/LAEDC Workshop which will be organized as the virtual/online event on July 3, 2022, between 8:00am - 12:00pm (local MX time) as an in-person event in Puebla (MX) providing an opportunity to meet with modeling engineers and researchers from Europe and Latin America.

The final program of the 5th International MOS-AK/LAEDC Workshop is available online:

https://www.mos-ak.org/puebla_2023/

Online Event Registration is open; any related enquiries can be sent to registration@mos-ak.org or laedc@ieee.org 

Important Dates: 

• Final Workshop Program: June 2023
  
• MOS-AK: July 2, 2023, Puebla (MX)
• 8:00am -  12:00pm (local MX time) MOS-AK Workshop

W.Grabinski for Extended MOS-AK Committee

WG210623

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/mos-ak/CALp-Rj-DstFXM-h9S78FZ_k5kKj9oJXYV%3Dz_vGRgPzz0XnqP%3DQ%40mail.gmail.com.

[book] Device Circuit Co-Design Issues in FETs

Device Circuit Co-Design Issues in FETs

Editors: Shubham Tayal, Billel Smaani, Shiromani Balmukund Rahi, Samir Labiod, Zeinab Ramezani

ISBN 9781032414256280 Pages 269 B/W Illustrations 

August 22, 2023 by CRC Press

Description

This book provides an overview of emerging semiconductor devices and their applications in electronic circuits, which form the foundation of electronic devices. Device Circuit Co-Design Issues in FETs provides readers with a better understanding of the ever-growing field of low-power electronic devices and their applications in the wireless, biosensing, and circuit domains. The book brings researchers and engineers from various disciplines of the VLSI domain together to tackle the emerging challenges in the field of engineering and applications of advanced low-power devices in an effort to improve the performance of these technologies. The chapters examine the challenges and scope of FinFET device circuits, 3D FETs, and advanced FET for circuit applications. The book also discusses low-power memory design, neuromorphic computing, and issues related to thermal reliability. The authors provide a good understanding of device physics and circuits, and discuss transistors based on the new channel/dielectric materials and device architectures to achieve low-power dissipation and ultra-high switching speeds to fulfill the requirements of the semiconductor industry. This book is intended for students, researchers, and professionals in the field of semiconductor devices and nanodevices, as well as those working on device-circuit co-design issues.

Table of Contents

1. Modeling for CMOS Circuit Design. 

2. Conventional CMOS Circuit Design. 

3. Compact modeling of junctionless Gate-All-Around MOSFET for circuit simulation. 

4. Novel Gate-Overlap Tunnel FETs for Superior Analog, Digital, and Ternary Logic Circuit Applications. 

5. Phase Transition Materials for Low Power Electronics. 

6. Impact of total ionizing dose effect on SOI-FinFET with spacer engineering. 

7. Scope and Challenges with Nanosheet FET based Circuit design. 

8. Scope with TFET based Circuit and System Design. 

9. An overview of FinFET based Capacitorless 1T-DRAM. 

10. Literature Review of the SRAM Circuits Design Challenges. 

11.Challenges and Future Scope of Gate-All-Around (GAA) Transistors: 

Physical Insights of Device-Circuit Interactions. 

[review] TCAD Simulations of Semiconductor Piezoresistance

Takaya Sugiura, Kazunori Matsuda*, Nobuhiko Nakano

Review: Numerical Simulations of Semiconductor Piezoresistance for Computer-Aided Designs

in IEEE J-EDS, vol. 11, pp. 325-336, 2023

DOI: 10.1109/JEDS.2023.3281866

  Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa, Japan

* Division of Electrical, Electronic and Infocommunications Engineering, Osaka University, Suita, Japan

Abstract: The field of piezoresistance has mainly advanced through experimental research; however, the improved accuracy of simulations and the emergence of new materials have increased the importance of simulations in this field. This review discusses the methods and current topics related to simulations of piezoresistive devices. Advancing simulation modeling will facilitate the computer-aided design of piezoresistive devices, and this review introduces the means of establishing these models by discussing the current studies on simulations and calculations in this field. Two simulation methods currently exist namely, device simulations and first-principles theoretical analysis. This review focuses on numerical simulation approaches for modeling of the piezoresistive effect using the multiphysics simulations of the mechanical and electrical behaviors of piezoresistive materials.

FIG: Basic simulation flow for studies on semiconductor piezoresistors.

[paper] Vertical Junction-Less Nanowire FETs

C. Maneux (University of Bordeaux), C. Mukherjee (CNRS), M. Deng (University of Bordeaux), G. Larrieu (CNRS), Y. WANG, B. Wesling, and H. Rezgui (University of Bordeaux)

Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

H02-1863 (Invited) at 243rd ECS Meeting and SOFC-XVIII 

Boston, MA, May 29 - June 2, 2023

Abstract: In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models

Fig: Final verification using full 3D multiphysics device thermal simulation, accounting for both ballistic and diffusive heat flux