[paper] Vertical Junction-Less Nanowire FETs

C. Maneux (University of Bordeaux), C. Mukherjee (CNRS), M. Deng (University of Bordeaux), G. Larrieu (CNRS), Y. WANG, B. Wesling, and H. Rezgui (University of Bordeaux)

Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

H02-1863 (Invited) at 243rd ECS Meeting and SOFC-XVIII 

Boston, MA, May 29 - June 2, 2023

Abstract: In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models

Fig: Final verification using full 3D multiphysics device thermal simulation, accounting for both ballistic and diffusive heat flux