[Si2 CMC] to Standardize SPICE Model for SiC MOSFET

May 03, 2021 // By Peter Clarke [eenewsanalog.com] 

The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.

Silicon-carbide offers higher efficiency and faster operation than silicon and has been adopted for several power applications including photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution. A CMC working group will oversee the model development with Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys set to participate.

"I'd encourage companies with a stake in silicon-carbide devices to join this effort and help guide selection of the model which best represents their intended use," 

advised Peter Lee, chair of the CMC.

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability [Read more...]

[paper] FET Library for VLSI

Taehak Kim¹, Jaehoon Jeong², Seungmin Woo², Jeonggyu Yang¹, Hyunwoo Kim² Ahyeon Nam², Changdong Lee², Jinmin Seo², Minji Kim², Siwon Ryu², Yoonju Oh², and Taigon Song¹,²  

NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes 

IEEE ISCAS, 2021, pp. 1-5, DOI 10.1109/ISCAS51556.2021.9401055.

¹School of Electronics Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea
²School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu 41566, South Korea

Abstract: Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology. 

Fig: Projected 3nm NSFET library development flow. Upper side of each step shows the names of required tools. Each colored-boxes correspond to the steps required for specific tasks: The blue boxes - device development, the orange boxes - digital design, and the green boxes - back end design, respectively.

Acknowledgements: This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2020M3H2A1078045). The EDA tool was supported by the IC Design Education Center(IDEC), Korea. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No.2019R1G1A109470212).

[paper] Compact modeling of lab-on-chip

Alexi Bonament, Morgan Madec and Christophe Lallement

Compact modeling of reaction-diffusion-advection mechanisms 

for the virtual prototyping of lab-on-chip 

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5,

doi: 10.1109/ISCAS51556.2021.9401396.

*Laboratory of Engineer Sciences, Computer Science and Imagine (ICube), UMR 7357 (Université de Strasbourg / Centre National de Recherche Scientifique), Strasbourg

Abstract: The topic of this paper is the development of compact models reaction-advection-diffusion phenomenon compatible with a SPICE simulation environment. From a mathematical perspective, biological systems that involve such phenomena are described by partial differential equations, which are not naturally handeled by SPICE. Our approach consists of discretizing these equations according to the finite-difference method and converting the resulting set of ordinary differential equations into an assembly of elementary equivalent electronic circuits written in Verilog-A. The main interest of this approach is the capability of coupling such models with third-party SPICE models of electronic circuits, sensors and transducers as well as biochemical models that can also be written in SPICE. The tool is validated both on simple problems for which analytical solutions are known and by comparison with a finite element simulator of reference

Fig: Core modules of the designed tool. Labels indicate the programming language.

Acknowledgment: This research was supported by the European Regional Development Fund (ERDF) and the Interreg V Upper Rhine Offensive Sciences Program (Project 3.14 – Water Pollution Sensor).

[paper] Dynamic Simulation of a-IGZO TFT Circuits Using AFCM

Y. Hernández-Barrios¹, J. N. Gaspar-Angeles¹, M. Estrada¹, B. Íñiguez², And A. Cerdeira¹

Dynamic Simulation of a-IGZO TFT Circuits Using the Analytical Full Capacitance Model (AFCM)

IEEE Journal of the Electron Devices Society, vol. 9, pp. 464-468, 2021, 

doi: 10.1109/JEDS.2020.3045347

1 SEES, Departamento de Ingeniería Eléctrica, CINVESTAV-IPN, Mexico City 07360, Mexico
2 Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, URV, Tarragona 43007, Spain

Abstract: The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present in bottom-gate AOSTFT structures. The dynamic behavior of the simulated circuit, when the TFT internal capacitances are increased or decreased and for different supply voltages of 10, 15 and 20 V, is compared with measured characteristics, obtaining a very good agreement. Afterwards, the AFCM is used to simulate the dynamic behavior of a pixel control circuit for a light emitting diode active matrix display (AMOLED), using an AOSTFT.

FIG: Fabricated and measured 19-stages Ring Oscillator (RO)

of amorphous oxide semiconductors (AOS) thin film transistors (TFTs) 

Aknowlwgement: This work was supported in part by the Consejo Nacional de Ciencia y Tecnología (CONACYT) under Project 237213 and Project 236887; in part by the H2020 program of the European Union under Contract 645760 (DOMINO); in part by contract “Thin Oxide TFT SPICE Model” with Silvaco Inc., under Grant T12129S; and in part by ICREA Academia 2013 from ICREA Institute and the Spanish Ministry of Economy and Competitiveness under Project TEC2015-67883-R GREENSENSE.

 

[paper] Does the Threshold Voltage Extraction Method Affect Device Variability?

Gabriel Espiñeira; Antonio J. García-Loureiro; Natalia Seoane

Does the Threshold Voltage Extraction Method Affect Device Variability?

IEEE J-EDS, vol. 9, pp. 469-475, 2021,

DOI 10.1109/JEDS.2020.3046122.

* CITIUS, Universidade de Santiago de Compostela, Galicia, Spain

Abstract: The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( VTH ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in VTH and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the VTH distribution ( σVTH ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the VTH extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

FIG: General capabilities of the FoMPy library [1]. FoMPy is able to import your data into a dataset, and after optional conditioning (data filtering or interpolation) is able to extract and plot some of the most commonly studied FoMs.

This work was supported in part by the Spanish Government under Grant PID2019-104834GB-100 and Grant RYC-2017-23312, and in part by the Xunta de Galicia and FEDER (accreditation 2016–2019) under Grant GRC 2014/008, Grant ED431G/08, and Grant ED431F-2020/008.

REF:

[1] FoMpy: A figure of merit extraction tool for semiconductor device simulations <https://github.com/gabrielesp/FoMpy>

[2] VENDES. A.J.Garcia-Loureiro, N.Seoane, M.Aldegunde, R.Valin, A.Asenov, A.Martinez and K.Kalna “Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors”, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, June 2011 doi=10.1109/TCAD.2011.2107990

[3] G.Espiñeira, N.Seoane, D.Nagy, G.Indalecio and A.J.García Loureiro, “FoMPy: A figure of merit extraction tool for semiconductor device simulations” in 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) doi:10.1109/ULIS.2018.8354752

[4] G.Espiñeira, D.Nagy, G.Indalecio, A.J.García Loureiro and N.Seoane, “Impact of threshold voltage extraction methods on semiconductor device variability” Solid-State Electronics, Volume 159, 2019, Pages 165-170, https://doi.org/10.1016/j.sse.2019.03.055