EU Goal: Reach 20% World-Share in Chip Manufacturing by 2020

EU to spend € 10 billion to trigger € 100 billion investments — SEMI provides the platforms for our members to share critical implementation issues and actions to support the goals set by the EU [H. Kundert, president, SEMI Europe] 

The new European industrial strategy for micro- and nano-electronics, published on 23 May 2013, sets the framework for targeted investment across the electronics value and innovation chain. An Industrial Strategy Roadmap for Investment, to be developed by end 2013, will cover three complementary lines:

• Transition to 450mm, expected to primarily benefit equipment and material manufacturers in Europe
• “More than Moore” on 200mm and 300 mm
• “More Moore” for ultimate miniaturization on 300mm wafers

Investment will be concentrated, focusing on Europe’s clusters of excellence in manufacturing and design (Grenoble, Dresden and Eindhoven-Leuven), but will also support partnerships and alliances across the value chain in Europe.

[read more...] also don't miss the SEMICON Europa 2013 Call for Papers (open until June 27). The conferences are a great opportunity to present your technology and latest achievements to a large audience of industry professionals. For more information about SEMICON Europe programs, the Call for Papers and opportunities to exhibit and present your products please go online and visit semiconeuropa.org.

Jobs for compact modelling specialists

Some jobs I've found while surfing the internet: (remember, we're not offering these jobs, only commenting on them!!).

(look at http://www.semiconductorjobs.com/a/jobs/find-jobs/q-compact+model+device for more information).

May 30	Modeling Engineering Manager	TriQuint Semiconductor US	Richardson, TX
	device characterization measurement, device model parameter extraction, and model ... product design. Produce and maintain 'compact' models for GaAs and GaN RFIC... more
May 05	Spice Modeling Engineer	Globalfoundries	California
	experienced Spice modeling engineer in the Compact Modeling & Characterization (CMC) ... Working closely with lab engineers on the device characterization (DC/AC/Transient/RF),... more
Mar 26	Compact Device Modeling Engineer	Intel	Hillsboro, OR
	Title: Compact Device Modeling Engineer Location: USA-Oregon, Hillsboro Job Number: 705850 ... * Developing and maintaining compact device models in internal circuit... more

May 30	Senior Software Architect	Xilinx	San Jose, CA
	Candidate will work in Device Modeling group in FPGA Implementation tools division of ... and coming up with new algorithms and compact data structures to represent Xilinx... more
May 23	Tcad device engineer Job	Micron	Boise, ID
	In this position, you will be studying detailed process and device design/optimization usi ... - Experience/knowledge in CMOS process, deep submicron device physics, state of the art mo... more

May 17	Staff Engineer		Santa Clara, CA
	special needs in device modeling (e.g. device measurement, reliability stress, and ... Knowledge in numerical device/process simulation and chip level extraction is a plus. more
May 15	Compact Device Modeling Engineer Job	Intel	Hillsboro, OR
	involves developing state-of-the-art compact device models and working in a highly ... - Developing and maintaining compact device models in internal circuit... more

[mos-ak] Si2 Announces Acquisition of the Compact Model Council

Standard SPICE Models, API, and Language Foundational to Industry

AUSTIN, Texas — (BUSINESS WIRE) — May 31, 2013 — The Silicon Integration Initiative (Si2) has announced the acquisition of the Compact Model Council (CMC). The CMC, formed in 1996, develops and standardizes compact models of electronic devices used within commercial circuit simulators across the electronics industry, including virtually all SPICE-class simulation. The CMC will be renamed the Compact Model Coalition to blend with Si2's organizational structure. The CMC, represented by 37 member companies, supports 20 active subcommittees and has produced over a dozen widely-used standard device models, modeling API, and SPICE language standard.

Details of the transfer and future plans will be presented at the Design Automation Conference (DAC) to be held in Austin, TX from June 2-6. The first presentation will be at the Si2 25th Anniversary Luncheon Celebration on June 3, 12-1:30 PM in Room 9ABC in the Austin Convention Center. The luncheon is free of charge. Other presentations are scheduled in the Si2 Booth #1427 on the DAC exhibit floor at: June 4 - 10:30AM and 4:30PM, and June 5 - 1:30PM. More information on this and other Si2 events can be found at this link: http://www.si2.org/?page=1544

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[mos-ak] Workshop on Compact TFT Modeling for Circuit Simulation

Call for Papers
5th International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation (CTFT)
CEA-LITEN, MINATEC Campus, Grenoble, France, June 21, 2013

In recent years, the increasing use of active matrix flat-panel displays and bio-medical imagers in commercial electronic products has drawn a significant attention to thin-film transistors (TFT) and technologies. TFTs on amorphous- and poly-silicon as well as newly emerging organic, transparent metal oxide and nano-composite semiconductor technologies are becoming increasingly common. For example, flat panel displays are finding widespread use in many products such as cellular phones, personal digital assistants (PDAs), camcorders, laptop personal computers (PCs), to name a few. The active matrix display is composed of a grid or matrix of picture elements called as "pixels". Thousands or millions of these pixels together create an image on the display, in which the TFTs act as switches to individually turn each pixel. More increasingly TFTs are starting to be used as analog circuit elements for rudimentary signal conditioning. Therefore, physically-based compact modeling of TFTs for circuit simulation is crucial to accurately and reliably predict TFT behavior in the active matrix. A concentrated R&D effort is critical for developing physically-based compact TFT models for emerging thin-film technologies, and significant R&D efforts along these lines are underway world-wide.

The CTFT workshop will provide a forum for discussions and current practices on compact TFT modeling. The 2013 CTFT workshop edition will be held on June 21 in Grenoble (France) in combination with the 9th International Conference on Organic Electronics (ICOE, June 18-20, www.icoe2013.org ). The CTFT workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in joint collaboration with CEA-LITEN, the Universitat Rovira i Virgili (Tarragona Spain) and the University of Cambridge (UK).

A partial list of the areas of interest includes:

• Physics of TFTs and operating principles
  
• Compact TFT device models for circuit simulation
  
• Model implementation and circuit analysis techniques
  
• Model parameter extraction techniques
  
• Applications of compact TFT models in emerging products
  
• Compact models for interconnects in active matrix flat panels

Abstract (500 Word) Submission deadline:  May 24, 2013
Prospective authors should submit a 500-word abstract to: Bogdan Mihai Nae (nae.bogden@urv.cat)
Submission of a 1-page or 2-page single-column paper to be included in proceedings: June 8, 2013.
Download the word template here for the 1-page or 2-page final version of the paper.

 

Committee Members      

Anis Daami, CEA-LITEN, France (General Co-Chair)	François Templier, CEA-LITEN, France (General Co-Chair)
Vincent Fischer, CEA-LITEN, France	Arokia Nathan, Cambridge University, UK
Benjamin Iniguez, Universitat Rovira i Virgili, Spain	Jamal Deen, McMaster University, Canada
Bill Milne, Cambridge University, UK	Andre Sazonov, University of Waterloo, Canada
John Robertson, Cambridge University, UK	Xiaojun Guo, Shanghai Jiaotong University, China
Flora Li, Polymer Vision, The Netherlands	Hyun Jae Kim, Yonsei University, Korea
Samar Saha, Silterra Corp., USA	Zhou Xing, Nanyang Technological University, Singapore
Norbert Fruehauf, University of Stuttgart, Germany	Peyman Servati, University of British Columbia, Canada
Man Wong, HKUST, Hong Kong

 

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[mos-ak] [Call for Papers] 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop Sept. 20, 2013 Bucharest

Together with the Organizing Committee and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the 11th MOS-AK/GSA ESSDERC ESSCIRC Workshop on Sept. 20, 2013 in Bucharest (RO). The event will open next decade of enabling compact modeling R&D exchange.

Topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• CM of passive, active, sensors and actuators
• Emerging Devices, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies

In the terms of participation, intending participants and authors should also note the following dates: 

• Call for Papers - May 2013
• 2nd Announcement - June 2013
  
• Final Workshop Program - July, 2013
• MOS-AK/GSA Workshop - Sept. 20, 2013
  

Free early registration: <http://www.mos-ak.org/bucharest/registration.php>

Abstract on-line submission <http://www.mos-ak.org/bucharest/abstracts.php>

Further details and updates: <http://www.mos-ak.org/bucharest/> 
Email contact: <workshops@mos-ak.org> 

- with regards - WG (for the MOS-AK/GSA Committee) 

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