Apr 2, 2020

#paper Y. Liao et al., "A Compact Model of Analog RRAM With Device and Array Nonideal Effects for Neuromorphic Systems," in IEEE TED, vol. 67, no. 4, pp. 1593-1599, April 2020 https://t.co/G0ciHLCNTt https://t.co/4Kb3pjIjoK


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April 02, 2020 at 11:41AM
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EDS Newsletter [April 2020 Vol. 27, No. 2 Issn: 1074 1879]

EDS Newsletter [April 2020 Vol. 27, No. 2 Issn: 1074 1879]
Delivered by Newsletter Editorial Staff led 
by Dr. Daniel Tomaszewski, ITE, Editor-In-Chief
pic.twitter.com/jXUEaD4p8I
— Wladek Grabinski (@wladek60) April 2, 2020
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April 02, 2020 at 09:37AM via IFTTT

Apr 1, 2020

Time to #OpenSource #Ventilators from Digital and Cyberspace Policy Program and Net Politics https://t.co/yum408VAoo https://t.co/j1ufYLxwAk


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April 01, 2020 at 08:28PM
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[C4P] ESSDERC TRACK3 Compact Modeling


European ESSDERC/ESSCIRC conference will be organized in Grenoble (F) on Sept.14-18, 2020 with its integral TRACK3: Compact Modeling and Process/Device Simulation which is open for submissions, now. You and all your R&D partners are welcome to submit a modeling paper. The paper submission deadline is April 17, 2020

TRACK3: Compact modeling and process/device simulation (including TCAD and advanced simulation techniques and studies)  focuses on following domains among other R&D topics:
  • Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. 
  • Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, HV and Power, emerging technologies and novel devices)
  • Compact/SPICE parameter extraction
  • Performance evaluation and open source (FOSS) benchmarking/implementation methodologies
  • Modeling of interactions between process, device and circuit design, 
  • Foundry/Fabless interface strategies
  • Numerical TCAD, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration
  • Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, ...)
  • Optical, mechanical or electro-thermal modeling and simulation
  • DfM, ageing, reliability of materials and devices
Please share our TRACK3 C4P with all your academic and industrial R&D partners active in the compact/SPICE modeling, Verilog-A standardization and TCAD/EDA simulations. Of course, your and your research team proactive contribution to our TRACK3 is more than welcome. I do hope that despite of a last minute notice, with your help, we will be able to draw even more attention to the ESSDERC/ESSCIRC Conference and, in particular, our modeling TRACK3



Mar 31, 2020

#paper: Bootsma, G.J., Nordström, H., Eriksson, M. and Jaffray, D.A., 2020. Monte Carlo kilovoltage X-ray tube simulation: A statistical analysis and compact simulation method. Physica Medica, 72, pp.80-87 https://t.co/9C1S4Y3023 https://t.co/D7RzqFb7tP


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March 31, 2020 at 09:18PM
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#COVID-19 Related Research and Technologies #Free to Access in #IEEE #Xplore https://t.co/8wtkdHydcI #paper https://t.co/kKCTCwfSCt


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March 31, 2020 at 02:50PM
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Professional #Ventilator Design #OpenSource Today by #Medtronic https://t.co/YkzX6fpU80 https://t.co/KA23i6RVDJ


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March 31, 2020 at 11:01AM
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Mar 30, 2020

#paper: N. Zagni et al. "Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs," in IEEE TED, vol. 67, no. 4, pp. 1560-1566, April 2020. https://t.co/wtk1U4sFuB https://t.co/xWzZ5GnQal


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March 30, 2020 at 05:01PM
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#paper: X. Li, T. Pu, L. Li and J. Ao, "Enhanced Sensitivity of GaN-Based Temperature Sensor by Using the Series Schottky Barrier Diode Structure," in IEEE EDL, vol. 41, no. 4, pp. 601-604, April 2020 https://t.co/koGfb8GeST https://t.co/LCE1l2wdly


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March 30, 2020 at 11:14AM
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conference paper reached 700 reads

M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion," 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 1-4.

Abstract: Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.

#paper Y. Nakamura, N. Kuroda, T. Yanagi, H. Sakairi and K. Nakahara, "High-Voltage and High-Current Id–Vds Measurement Method for Power Transistors Improved by Reducing Self-Heating," in IEEE EDS (Open Access), vol. 41, no. 4, pp. 581-584, April 2020. https://t.co/85eA0jPQKb https://t.co/PT6CUQRELM


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March 30, 2020 at 09:52AM
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Mar 29, 2020

#paper: T. Mikolajick, U. Schroeder and S. Slesazeck, "The Past, the Present, and the Future of Ferroelectric Memories," in IEEE TED, vol. 67, no. 4, pp. 1434-1443, April 2020. https://t.co/OmPJ0xf6wU https://t.co/jWifCPdJ1D


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March 29, 2020 at 06:08PM
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#paper: Scientists from the POWERlab at #EPFL, have built a nanodevice capable of producing high-power Terahertz (#THz) waves https://t.co/Cl6jBInynx https://t.co/4PIJmN6Jpm


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March 29, 2020 at 05:38PM
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#paper: EKV Transistor Model For Ultra Low-Voltage Bulk-Driven Circuits


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March 29, 2020 at 04:33PM
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Mar 27, 2020

The Art of Reverse Engineering appeared first on #OpenSource For You https://t.co/B1sKAzlzAh https://t.co/OZ4ErMqS0Y


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March 27, 2020 at 04:44PM
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#paper: Q. Huo et al., "A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond," in IEEE J-EDS, vol. 8, pp. 295-301, 2020 DOI: 10.1109/JEDS.2020.2980441 https://t.co/QrqdHdvHmT https://t.co/vTr39EBQ6r


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March 27, 2020 at 10:23AM
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100 #wafer #fabs taken out of production in the last decade https://t.co/wtWEahOHfF #paper https://t.co/FVBSYTOYld


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March 27, 2020 at 09:46AM
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[blog] Image Sensors World

blog shares news and discussions about image sensors

Read 5 Recent Comments:
I think the FOV of the ST Micro Lidar is too narro... - 3/27/2020 - Anonymous
Announced to the press but ST page lists them as &... - 3/26/2020 - Anonymous
Who is supplying this LIDAR Scanner? - 3/26/2020 - Anonymous
"from the financial sector than a biological ... - 3/26/2020 - Anonymous
Is this the STMicroelectronics MEMS lidar? Or what... - 3/25/2020 - Dharmaone

Since the end of January, the #opensource community has contributed to thousands of open source repositories that mention coronavirus or #COVID-19 https://t.co/VsVksULG6l https://t.co/096vvMt3Ed


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March 27, 2020 at 09:07AM
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Mar 24, 2020

#paper A. A. Zope, J. Chang, T. Liu and S. Li, "A CMOS-MEMS Thermal-Piezoresistive Oscillator for Mass Sensing Applications," in IEEE TED, vol. 67, no. 3, pp. 1183-1191, March 2020 doi: 10.1109/TED.2020.2969967 https://t.co/A1UCrpxzZw https://t.co/7cm4KbfWMn


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March 24, 2020 at 05:59PM
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#paper: A. Yesayan, F. Jazaeri and J. Sallese, "Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs," in IEEE TED, vol. 67, no. 3, pp. 1157-1164, March 2020 doi: 10.1109/TED.2020.2965167 https://t.co/ZQqam0Idam https://t.co/fLVyDK5rfB


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March 24, 2020 at 04:29PM
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#paper M. H. Mohamed Sathik, P. Sundararajan, F. Sasongko, J. Pou and S. Natarajan, "Comparative Analysis of IGBT Parameters Variation Under Different Accelerated Aging Tests," in IEEE TED, vol. 67, no. 3, pp. 1098-1105 doi: 10.1109/TED.2020.2968617 https://t.co/pcQI7dpLeO https://t.co/9Sz1Vqnaf2


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March 24, 2020 at 11:15AM
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#paper: W. Chen, J. Cheng and X. B. Chen, "A Novel IGBT With High-k Dielectric Modulation Achieving Ultralow Turn-Off Loss," in IEEE TED, vol. 67, no. 3, pp. 1066-1070, March 2020 doi: 10.1109/TED.2020.2964879 https://t.co/uoh7n0NYFa https://t.co/wdqFNSMBur


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March 24, 2020 at 10:24AM
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Mar 23, 2020

[paper] Charge-based Modeling of Ultra Narrow Cylindrical Nanowire FETs

Charge-based Modeling of Ultra Narrow Cylindrical Nanowire FETs 
Danial Shafizade, Majid Shalchian and Farzan Jazaeri
IEEE TED, Vol. XX, No. XX, 15 March 2020

Abstract: This brief proposes an analytical approach to model the dc electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistor (JLNW-FET). The model includes explicit expressions, taking into account the first order perturbation theory for calculating eigenstates and corresponding wave functions obtained by the Schrodinger equation in the cylindrical coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step toward the analysis of circuits mainly biosensors based on junctionless nanowire transistors.

MicroTec: Semiconductor Process and Device Simulator

Software Package for 2D Process and Device Simulation
Version 4.0 for Windows
User’s Manual
Publisher: Siborg Systems Inc
Editor: Michael S. Obrecht

MicroTec allows 2D silicon process modeling including implantation, diffusion and oxidation and 2D steady-state semiconductor device simulation like MOSFET, DMOS, JFET, BJT, IGBT, Schottky, photosensitive devices etc. Although MicroTec is significantly simplified compared to widely available commercial simulators, it nevertheless is a very powerful modeling tool for industrial semiconductor process/device design. In many instances MicroTec outperforms existing commercial tools and it is remarkably robust and easy-to-use.

FIG: MicroTec SibGraf GUI windows




#paper: J. N. Ramos-Silva, A. Pacheco-Sinchez, M. A. Enciso-Aguilar, D. Jimenez, E. Ramirez-Garcia: Small-signal parameters extraction and noise analysis of CNTFETs, IOPscience SST 35(4), 045024 (Mar 2020) doi:10.1088/1361-6641/ab760b https://t.co/vY5g9t4h1B https://t.co/L00nT1AkMS


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March 23, 2020 at 11:01AM
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Mar 19, 2020

#XFAB Further Expands its #SiC Capacity and Adds New In-House Epitaxy Capabilities https://t.co/1ZecCr6k92 #paper https://t.co/5RCDzb1cbv


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March 19, 2020 at 11:30AM
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[paper] Negative Capacitance Double-Gate JunctionlessFETs


Negative Capacitance Double-Gate JunctionlessFETs: A Charge-based Modeling Investigation of Swing, Overdrive and Short Channel Effect
Amin Rassekh, Jean-Michel Sallese, Farzan Jazaeri, Morteza Fathipour and Adrian M. Ionescu
IEEE TED, Vol. XX, No. XX, March 3, 2020

Abstract: In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectricon the I-V characteristics. Importantly, for the first time,our model predicts that the negative capacitance minimizes short channel effects and enhances current over-drive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels (0.1 μA/μm). Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.
Fig: The difference of the potential across the ferroelectric (left axis) and the difference of total charge density of ferroelectric (right axis) in high VDS and low VDS versus the channel length. ∆Vf somehow represents ∆VG (The difference of VG in high and low VDS). The inset illustrates the schematic of the I-V characteristic of a regular double gate JLFET and a double gate JLFET with negative capacitance at low and high VDS.


Mar 18, 2020

#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS doi: 10.1109/JEDS.2020.2978400 https://t.co/FJVoSI3mJ5 https://t.co/3xiWGBvVcj


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March 18, 2020 at 02:47PM
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Mar 17, 2020