Showing posts with label modeling. Show all posts
Showing posts with label modeling. Show all posts

Aug 6, 2020

[chapter] Design of FET Biosensors

Khuraijam Nelson Singh1 and Pranab Kishore Dutta1
Chapter 8: Analytical Design of FET-Based Biosensors
in Advanced VLSI Design and Testability Issues; Eds: Suman Lata et all.
CRC Press, 19 Aug 2020; 360 pages

1NERIST, Arunachal Pradesh, India

Abstract: Research on biosensors has seized the interested researchers over the past few decades due to their various advantages and applications. They are used in the discovery of drugs, monitoring of diseases, agriculture, food quality control, industrial wastage monitoring, military, etc. The sensing analyte is the main element that differentiates a biosensor from the other physical/chemical sensors. In general, the biosensor is a device that is used to detect an analyte using a biosensitive receptor. Its main components are as follows:
  • Analytes: The substance that is intended to be detected, such as glucose in a glucose sensor, ammonia in ammonia sensor, and so on.
  • Bioreceptors: The bioreceptors are biosensitive elements used to detect target analytelbiomolecule. They are sensitive to the analytes of interest. Some examples of bioreceptors are antigen, DNA, enzyme, and so on.
  • Transducers: The elements that are used to convert energy from one form to another are called transducers. In a biosensor, the interaction of analytes and bioreceptors produces changes in the form of heat, gas, light, ions, or electrons. These changes are then converted into a quantif‌iable form by the transducer. Usually, the output of the transducer is in the form of electrical or optical signals, and the generated signal is proportional to the interaction between the analyte and the biosensor.
FIG: Schematic diagram of ion-sensitive f‌ield-effect transistor (ISFET)

Jul 20, 2020

[C4P] Advanced FETs: Design, Fabrication and Applications

Call for Papers: Special MDPI  Issue 
"Advanced Field Effect Transistors: Design, Fabrication and Applications"
Deadline for manuscript submissions: 31 July 2021.

Dear Colleagues,
Planar MOS Field Effect Transistors (MOSFETs) were invented by Atalla and Kahng in 1959. After a decade, the MOSFETs entered mass production, as basic building blocks of P-, N-, and CMOS integrated circuits (ICs). Until the end of the twentieth century, MOSFET performance was largely improved by the implementation of so-called scaling rules. An exponential growth in the time of the transistor number per chip (observation formulated as Moore law) was achieved. This, together with advantageous characteristics and a nice feature of the planar MOSFETs allowing one to design the ICs by defining a width/length ratio, led to the great success of the CMOS technology on Si and SOI substrates.
However, starting from the 90 nm node, it has been observed that the standard scaling does not sufficiently translate into MOSFET performance improvement. Moreover, some device characteristics become degraded, e.g. gate leakage, channel leakage, variability and reliability. This has led to the development of preventative measures (e.g. high-k dielectrics) or performance boosters (e.g. channel strain engineering and channel materials). Furthermore, 2D and 3D multi-gate FETs were introduced to improve gate control over the channel and increase the channel aspect ratio. Multi-gate FETs are the only option for the 5nm node, which is expected soon, whereas they will have to be replaced by surrounding gate FETs for the 3nm node. For the past few years, the attention of researchers has been attracted by steep-subthreshold slope devices, enabling the reduction of supply voltage. A need for devices for quantum computing has appeared. FETs and HEMTs, for very high frequency applications, GaN, SiC and FETs for high voltage, high power, high temperature applications, and many other FET types, are in use or under development as a micro- and nanoelectronics reply to electronics needs in different domains.
There are many issues regarding the design, fabrication and applications of advanced field effect transistors. It is my pleasure to invite you to share your expertise in this Special Issue. Full papers, communications and reviews are all welcome.

Dr. Daniel Tomaszewski, ITE, Warsaw (PL)
Special Issue Guest Editor

[read more...]

Mar 23, 2020

MicroTec: Semiconductor Process and Device Simulator

Software Package for 2D Process and Device Simulation
Version 4.0 for Windows
User’s Manual
Publisher: Siborg Systems Inc
Editor: Michael S. Obrecht

MicroTec allows 2D silicon process modeling including implantation, diffusion and oxidation and 2D steady-state semiconductor device simulation like MOSFET, DMOS, JFET, BJT, IGBT, Schottky, photosensitive devices etc. Although MicroTec is significantly simplified compared to widely available commercial simulators, it nevertheless is a very powerful modeling tool for industrial semiconductor process/device design. In many instances MicroTec outperforms existing commercial tools and it is remarkably robust and easy-to-use.

FIG: MicroTec SibGraf GUI windows




Jul 8, 2019

Leti Workshop at SISPAD 2019

Leti is pleased to invite you to attend our ‘Advanced Simulations for Emerging Non-Volatile Memory Technologies’ seminar, which is organized as an official satellite event of the 2019 IEEE SISPAD Conference (http://www.sispad2019.org). By the proposed seminar, we will emphasize how simulation and modeling support memory technology developments and device behavior understanding.

This event will held on Tuesday, September 3rd from 5:00 PM to 7:30 PM, Palazzo di Toppo Wassermann, Università degli Studi di Udine, Udine, Italy (i.e. at the SISPAD 2019 conference location).
PROGRAM

  • Welcome and Introduction – T. Poiroux
  • Innovative non-volatile memory technologies: a revolution for the storage towards a memory that thinks – G. Navarro
  • Electro-thermal and material simulations for PCM – O. Cueto
  • Multiphase field method for the simulation of the complex phase changes in PCM – R. Bayle
  • Invited talk: Self-consistent TCAD simulation of chemical reactions within electronic devices. Application to CBRAM and OxRAM – Silvaco
  • Networking cocktail

Registration is free but, due to limited seats, please register just sending an email to thierry.poiroux@cea.fr and sebastien.martinie@cea.fr.

Feel free to share this invite with your colleagues !

Aug 3, 2017

Basics of MOSFET Modeling


Basics of MOSFET Modeling with LabVIEW/LTspice 
  • Introduction to MOSFET Models 
  • Functions and Parameter Extraction
  • visit http://mosfet-engineer.blogspot.com

Nov 11, 2016

ICNF 2017: 2nd Call for Papers

24th International Conference on Noise and Fluctuations (ICNF 2017) 
20-23 of June 2017 in Vilnius, Lithuania

We would like to invite you to submit your abstracts. For submission of the abstracts, please, REGISTER and go to the Abstract submission site. Instruction for authors and templates for abstract preparation can be found and downloaded  at the Conference website: http://www.icnf2017.ff.vu.lt/paper-submission/instructions-for-authors
Deadline of the abstract submission is 22 January, 2017

Please also keep in mind ICNF2017 important dates:
  • Abstract submission deadline: 22 January, 2017
  • Notification of acceptance deadline: 27 February, 2017
  • Full paper submission deadline:27 March, 2017
  • Early bird registration: 19 April, 2017
  • Conference: 20-23 June, 2017
Please share this information to your colleagues and those who might be interested in ICNF 2017.

For more information visit the Conference website: http://www.icnf2017.ff.vu.lt/
or contact us: icnf2017@ff.vu.lt

Looking forward to meeting you in Vilnius.

With best regards,
Sandra Pralgauskaitė and Paulius Sakalas - Organizing Committee Chairs


Feb 7, 2016

Simulating the World’s Smallest Integrated Switch

This visualization from CSCS in Switzerland shows the world’s smallest integrated switch.

The switch is based on the voltage-induced displacement of one or more silver atoms in the narrow gap between a silver and a platinum plate.

Researchers working under Juerg Leuthold, Professor of Photonics and Communications at ETH Zurich, have created the world’s smallest integrated optical switch. Applying a small voltage causes an atom to relocate, turning the switch on or off. ETH Professor Mathieu Luisier, who participated in this study, simulated the system using Piz Daint Supercomputer. The component operates at the level of individual atoms. The team’s latest development was recently presented in the journal Nano Letters.