May 11, 2011
Spice simulation, Tina-TI, LTSpice, PSpice, and more
May 10, 2011
job offer at Mentor
May 7, 2011
π Raspberry Pi Foundation
May 6, 2011
Reflections from ISSCC 2011
TSMC not following Intel to Finfets at 22nm - waiting till 20nm
Celebrating engineering: EDN names 2010 Innovation Award winners
Category: EDA Tools and ASIC TechnologiesThe finalists in this category—Apache Design Solutions, GateRocket Inc, GlobalFoundries, and Mentor Graphic—are recognized for innovations in design automation tools that reduce cycle time, increase manufacturability, and improve the reliability of integrated circuits. "Tonight's winner has achieved two of the most difficult feats in the EDA industry," Technical Editor Mike Demler said. "First, it has a history of developing innovative, differentiated products. This latest innovation addresses the problem of simulating electro-static discharge that has challenged designers for many years. The second distinction is to leverage that success into a proposed IPO."
Winner: Apache Design Solutions
Intel And Seagate: Silicon Transistor And Magnetic Storage Density Maintain An Impressively Steady Improvement Rate - Brian's Brain | Blog on EDN
Two fundamental technology breakthroughs in two days; these are the times that tech editors dream of! I’ve in the past drawn a correlation between Moore’s Law (named for Intel’s Gordon), a forecast of the pace of single-chip transistor integration increase over time first made in 1965, and the rate of capacity growth over time (said another way, cost-per-capacity) for both magnetic and semiconductor storage. Solid-state drives, of course, are direct beneficiaries of Moore’s prescience, but areal density increases in magnetic storage are at least as impressive if not more so.
Apr 27, 2011
[mos-ak] MOS-AK/GSA Paris Workshop Press Release
Experts Share Insight on Compact Device Modeling with Emphasis on
Simulation-Aware Models
Press release: http://gsaglobal.org/news/article.asp?article=2011/0426
On-line publications: http://www.mos-ak.org/paris/
The MOS-AK/GSA Modeling Working Group has several upcoming events:
* special modeling session at the MIXDES Conference in Gliwice, Poland
(https://www.mixdes.org/Special_sessions.htm);
* autumn MOS-AK/GSA workshop in Helsinki, Finland;
* winter MOS-AK/GSA meeting in Washington, D.C., USA.
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
Apr 7, 2011
TSMC lays out their 20nm roadmap, no disruption from Japan.
TSMC kicked off their annual Technology Symposium series in San Jose today. Founder, Chairman and CEO Morris Chang opened the proceedings by addressing concerns for how Japan’s disaster recovery will impact the foundry’s supply chain. Dr. Chang listed a number of issues that had been of concern; metal sputtering targets, CMP (chemical-mechanical polishing) slurry, raw silicon wafers, chemicals, tools and spare parts. However, he assured the audience, TSMC has been able to solve all supply problems and “everything is under control, no supply shortages will interrupt the production lines“.
TSMC does expect an impact on their customers, however, and their customer’s customers. Dr. Chang said that there will be some effect on the industry in Q2 and possibly into Q3, but the impact would be no more than two quarters. This will add to a slight softening in the world economy; including Chinese efforts to fight inflation, problems in Europe, some economic measures in U.S., with the end result being that 2011 will be less strong than TSMC had originally thought. The company is resetting their forecast from 7% growth down to 4%.
Dr. Chang then went on to describe how the semiconductor market drivers have changed; from PCs (1980-2000), to cell phones (2000 - 2010), to today’s “killer app” - mobile products, including smartphones, tablets, and any “devices you carry around“.
Moving to more technical topics, Dr. Chang predicted that the 20nm process that they have in development will provide 2X the performance over 28nm. TSMC has also begun investigation at 14nm, and “Moore’s law still has some distance to go“, according to Chang. He also noted that the company has “significant R&D” in 3D IC technology; including 2/2.5D interposers, TSV (through-silicon vias), and what the company refers to as “system-level scaling“.
Dr. Chang concluded by comparing TSMC’s capacity (2 - 12″ fabs produce up to 260,000 wafers/month), to competitors, stating that they are building capacity but they don’t have the technology, that what competitors have is not “effective capacity“. TSMC is also working on production of 450mm wafers. Pilot production is targeted for 2013-14, with an “intercept point” for production of 20nm in 2015-16.
The 20nm roadmap
Next up on the morning’s agenda was Dr. Shang-Yi Chiang, TSMC’s Sr. VP R&D, to go over TSMC’s advanced technology roadmap. Looking out to the next process node, Dr. Chiang said that the 20nm (20G) process will be available in Q3 2012. In the meantime, TSMC will offer4 versions at 28nm; LP, HPL, G, and HPM. HPM will combine high performance and low power, the sweet spot for ARM cores according to Dr. Chiang.
Dr. Chiang said that the migration to a new process node typically adds 2-3 process modules, but 5 new modules are needed for 20nm. The 20nm process node will be the last generation for planar transistors. The most expensive 20nm process module will be the change to double patterning. TSMC has developed software that will automatically apply DFM requirements to create the 2nd mask from design data.
TSMC’s 20G and 20SoC processes will offer >2X the performance and <0.75X the switching power compared to 28HP & 28HPM. A 20nm SRAM has been fabricated, but 100% yield has not been achieved yet. At 20nm, TSMC is seeing a sidewall interface effect that can dominate interconnect delays, now that line widths are approaching the mean-free path of electrons. According to Dr. Chiang, TSMC has developed a smoothing process that minimizes the effect of electrons literally bouncing off of the walls of interconnect.
TSMC says that they are innovating to extend immersion lithography to 20nm, but that NGL (next-generation lithography) will be required for nodes <20nm. Dr. Chiang said that TSMC plans to have an ASML EUV machine, the NXE-3100 at TSMC by mid-2011.
Apr 1, 2011
Nano-KISS: Advanced CMOS Devices
Scientific Program nano-KISS 2011
Mar 22, 2011
Build accurate Spice models for low-noise, low-power precision amplifiers
Although higher-speed amplifiers have multiple poles and zeros, this model is for a single-pole, 10-MHz amplifier. It lets you simulate the amplifier’s key ac and dc parameters. The model includes ac parameters for flicker and flatband noise, slew rate, CMRR (common-mode rejection ratio), gain, and phase. The model’s dc parameters are VOS (input offset voltage), IOS (input offset current), quiescent supply current, and output-voltage swing. The model uses the 25°C typical parameters (Reference 2). The closer you model the input stage to the actual amplifier, the more accurate your results will be. You can achieve an accurate ac representation of the amplifier’s performance using a few of the process parameters of the input-stage transistors or MOSFETs. This model’s architecture lets you model amplifiers with split supplies. There is no ground reference in any of the signal-processing blocks. After the differential-to-single-ended conversion, all internally generated node voltages are referenced to the midpoint of the power supplies, much like the actual operation of an amplifier."
Complete IC simulation requires a full toolbox of hardware and software
Mar 16, 2011
[mos-ak] Final Program MOS-AK/GSA Workshop in Paris
program:
http://www.mos-ak.org/paris/
* Free On-line Registration Form:
http://www.mos-ak.org/paris/registration.php
* Venue:
Université Pierre et Marie Curie
LIP6 (UPMC)
4 Place Jussieu; Paris
Bâtiment ESCLANGON; Amphithéâtre ASTIER
* Agenda: 7-8 April 2011 MOS-AK/GSA Workshop
"Frontiers of the Compact Modeling for Advanced Analog/RF
Applications"
April 7 (13:00-16:00)
* half day/afternoon MOS-AK modeling session
* poster session introduction
* COMON Network meeting/session (members only)
* informal MOS-AK/COMON "modeling" dinner (individual selfpaid)
April 8 (9:00-16:00)
* morning MOS-AK Session
* poster session
* afternoon MOS-AK Session
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
Mar 14, 2011
Looking for Modeling & Characterization Engineer. Please send resume to Goldie.Homan@onsemi.com or apply Job 10536 at http://www.onsemi.com/PowerSolutions/content.do?id=16367
- Perform and analyze electrical measurements on various devices.
- Design test structures.
- Extract device SPICE models using ICCAP, UTMOST, MQA, and other in-house software packages.
- Support transfer methodology for models from TRD to Design Methodology.
- Document characterization and modeling work according to established procedures.
- Evaluate and support implementation of new characterization, modeling and methods.
- Provide performance assessment and feedbacks for device development engineering.
- Interface with Design Methodology, Design, Foundry and external customers to resolve characterization/modeling issues and improve characterization/modeling methods.
- Work jointly with modeling groups in CZ to perform characterization/modeling tasks.
- Perform other tasks as may be from time to time assigned.
Position Requirements Successful candidates for this position will have:
- A BS/MS/PhD in Electrical Engineering/Physics/Material Science/Chemical Engineering/Chemistry. MS/PhD preferred.
- In-depth understanding of semiconductor device physics and proficiency in DC, AC, and RF characterization.
- Previous Design/Device fabrication/Process integration experience desired.
- Ability to utilize statistical techniques is required.
- UNIX/LINIX shell, PERL programming experience is desired.
- Previous experience with BiPolar device design/simulation/modeling is a plus.
- Previous experience in RF parasitic extraction is a plus
- Demonstrated ability to work successfully with external groups is required.
Mar 13, 2011
NASA To Host Open Source Summit
Mar 2, 2011
SPICE: a 40-year old open-source success story
From EDN:
SPICE: a 40-year old open-source success storySPICE, the Simulation Program with Integrated Circuits Emphasis, has turned 40 years old. The IEEE has marked the occasion by designating the development of SPICE as a Milestone in Electrical Engineering and Computing. On February 23rd, the Computer History Museum hosted a celebration with a roundtable discussion by the individuals most responsible for bringing SPICE from its origin as a UC Berkeley student project to the huge commercial success it has achieved as the most widely used tool in the semiconductor industry.
The panel (from left to right) consisted of:
- Ron Rohrer - 2002 Kaufman Award recipient, who taught the class at UCB that developed the progenitor of SPICE, CANCER (Computer Analysis of Nonlinear Circuits, Excluding Radiation)
- Larry Nagel - as a student in Ron’s class, Larry took on CANCER as his Master’s degree project, and eventually developed the 1st successful implementation - SPICE2 - as his doctoral thesis.
- Kim Hailey - co-founder (with Shawn Hailey) of Meta-Software, where HSPICE was created.
- Ken Kundert - who led the development of Cadence’s Spectre simulator.
- David Hodges - Distinguished Professor Emeritus at UCB, the panel moderator, who is well known for leading the development of analog IC design in CMOS and for the original (Level-1) Shichman-Hodges MOS device model.
Read more.... in EDN
Feb 28, 2011
Analog/Mixed-Signal Behavioral Modeling
Analog/Mixed-Signal Behavioral Modeling – When to Use What
So when to use what? The conservative style provided by Verilog-A and Verilog-AMS is useful when there are significant accuracy requirements. This approach can potentially provide a 50-100X speedup over SPICE, but it all depends on how good your modeling is. "If you're a poor modeler, there's a chance you could end up with a model that's as slow as SPICE simulation or even slower," Walter warned.
Real number modeling, also available through Verilog-AMS with the wreal data type, brings real number values into event-driven digital simulation. It thus has the speed benefits of digital simulation and can leverage the metric-driven verification methodology that's increasingly used by digital engineers. It's good when there are hard performance requirements and limited accuracy requirements. For example, wreal is very useful for full-chip mixed-signal simulations.
The following chart shows the accuracy/speed tradeoff ranges provided by various analog/mixed-signal modeling alternatives. Note that the conservative modeling style has a broad possible range, depending on how good the modeling is.
Feb 25, 2011
Microelectronics Journal, in-press, february 2011
Md. Gaffar, Sayed Ashraf Mamuna, and Md. Abdul Matina
Available online 24 February 2011.
Abstract
In this paper, a three dimensional analytical solution of electrostatic potential is presented for undoped (or lightly doped) quadruple gate MOSFET by solving 3-D Poisson's equation. It is shown that the threshold voltage predicted by the analytical solution is in close agreement with TCAD 3-D numerical simulation results. Numerical simulation, self-consistent Schrodinger–Poisson equations, calibrated by 2D non equilibrium green function simulation, are used.
Feb 23, 2011
The First Full-Color Display with Quantum Dots
Rodrigo Picos (rpicosg@gmail.com*) has sent you an article from TechnologyReview.com! Click below to read the article: The First Full-Color Display with Quantum Dots If clicking on the title above does not work, paste the link below into your web browser: |
SPICE Circuit Simulator Named IEEE Milestone
[Read more by Anna Bogdanowicz @ IEEE]
Feb 15, 2011
Papers in SSE (vol 57 , issue 1, March 2011)
A. Tsormpatzoglou, D.H. Tassis, C.A. Dimitriadis, G. Ghibaudo, N. Collaert, G. Pananakakis
Generic complex-variable potential equation for the undoped asymmetric independent double-gate MOSFET
Adelmo Ortiz-Conde, Francisco J. García-Sánchez
Research highlights
► Single completely generic equation of channel potential for undoped asymmetric independently driven double-gate MOSFETs. ► Channel potential equation is based on complex variables and is valid for all values of front and back-gate bias. ► The unified nature of the proposed equation provides a better basis for global physical insight. ► Several examples, including the all important fully symmetric case, are analyzed.Compact modeling of CMOS transistors under variable uniaxial stress
Nicoleta Wacker, Harald Richter, Mahadi-Ul Hassan, Horst Rempp, Joachim N. Burghartz
Research highlights
► We propose a method to simulate the effect of uniaxial stress on MOSFETs. ► The method is valid for any drain current and stress directions in (001) Si plane. ► It can perform static and dynamic simulations, in linear and saturation regions. ► It is simulator-independent and does not depend on the source of uniaxial stress. ► It is adaptable to other bulk CMOS nodes and to other technologies such as SOI.A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation
F. Lime, R. Ritzenthaler, M. Ricoma, F. Martinez, F. Pascal, E. Miranda, O. Faynot, B. Iñiguez
Research highlights
► Valid for long-channel undoped ADGMOSFETS with independent gate operation. ► Fully analytical and explicit derivation with no iterative solutions. ► Accessible front and back gate charges, potentials and currents. ► Unification of symmetric and asymmetric cases. ► Physical solutions similar to classical MOS theory.In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation
B. Grandchamp, M.-A. Jaud, P. Scheiblin, K. Romanjek, L. Hutin, C. Le Royer, M. Vinet
Research highlights
► We performed 2D simulations of germanium-on-insulator fully-depleted pMOSFET. ► Interface traps, mobility and leakage were calibrated versus experimental data. ► The prediction of electrical characteristics is accurate for several gate lengths. ► These simulations help in finding guidelines for improving the on-state current.Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces
G. Hamaide, F. Allibert, F. Andrieu, K. Romanjek, S. Cristoloveanu
Research highlights
► Biasing the back interface in accumulation while extracting carrier mobility in FD-SOI MOSFETs leads to underestimated values. ► Apparent mobility degradation with decreasing film thickness in ultra-thin SOI MOSFET or Pseudo-MOSFET measurement is due to an additional component of the vertical electric field. ► In Pseudo-MOSFET measurements, the additional component of the vertical electric field comes from the traps and charges at the free-surface of the sample. ► We propose a new model to take this additional component of the vertical electric field into account.Feb 14, 2011
Is SPICE good enough for tomorrow's analog?
IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2010),
Digital Object Identifier: 10.1109/BIPOL.2010.5668096
Publication Year: 2010 , Page(s): 106 - 112
Feb 7, 2011
[mos-ak] C4P MOS-AK/GSA Workshop at UPMC/LIP6 Paris on 7-8 April 2011
http://www.mos-ak.org/paris/
Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
UPMC/LIP6 Paris on 7-8 April 2011
The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies
The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by MARCH.1st:
http://www.mos-ak.org/paris/abstracts.php
Intending authors should also note the following deadlines:
* Call for Papers - Feb.2011
* Notification of preliminary acceptance - March 2011
* Final Workshop Program - end of March 2011
* MOS-AK/GSA Workshop - 7-8 April 2011
Further details and updates http://www.mos-ak.org/paris/
On-line workshop registration http://www.mos-ak.org/paris/registration.php
Local Organizing Committee:
Marie-Minerve Louerat, UPMC/LIP6
Ramy Iskander, UPMC/LIP6
Technical Program Committee:
Marie-Minerve Louerat, UPMC/LIP6
Andrei Vladimirescu, ISEP/UCB
Costin Anghel, ISEP
Ramy Iskander, UPMC/LIP6
Extended MOS-AK/GSA Committee:
Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA)
Chelsea Boone, GSA; Director of Research
Kayal Rajendran, GSA; Senior Research Analyst
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Roberto Tinti, Agilent EEsof Division
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
Sergio Bampi, UFRGS, Brazil
Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Alexander Petr, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
James Victory, Sentinel-IC
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
A.B. Bhattacharyya, JIIT, India
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
IEEE SCV EDS: February 8 Photovoltaic Technology Talk
Feb 8th:
(Next month event) March 1st:
More information at the IEEE Santa Clara Valley EDS Chapter Home Page
http://www.ewh.ieee.org/r6/scv/eds/
Feb 3, 2011
Molybdenite touted as 'material to revolutionize electronics'
Jan 28, 2011
Postdoc position on compact device modeling in Spain
As Professor in the Universitat Rovira i Virgili (Tarragona, Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry under the Programa Juan de la Cierva) related to the European projects we participate in: the SQWIRE project (a project about technology, characterization and modeling of Si nanowires) and the Compact Modeling Network, COMON (of which I am the coordinator).
The candidate should be a person who holds a PhD as awarded within the three years prior to the date when the period for presentation of application forms closes. The Ph D must have been obtained later than January 1 2007. If the candidate does not hold a PhD yet, the deadline to be awarded a PhD is the date of publication of the Awarding Resolution in the Ministry of Education and Science web site.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the European projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects: nanowire FETs, multi-gate MOSFETs (FinFETs, DG MOSFETs,...), High Voltage MOSFETs and advanced HEMTs.
The postdoc position, which will be a contract, will have a duration of up to 3 years. The net salary will be around 1900 Euro/months.
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 8 2011
MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat
Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.
About Tarragona:
Tarragona is located on the Mediterranean, in the heart of the Costa Daurada, in the south of Catalonia, about 100 Km south from Barcelona. Tarragona is well connected to Barcelona by highway, and frequent trains and buses. It has also a direct bus connection with Barcelona Airport. Besides, it has high-speed rail connection with Madrid and Barcelona.
Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. F On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public. Among the citizens of Tarragona, it has moreover fomented knowledge of, pride in and respect for the city.
Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: “The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring.” Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe. The city has a population of 120,202 inhabitants, and the native tongue is Catalan, but everybody speaks also Spanish, which is also official in Catalonia. Many people can also speak English (especially the young people) or French.
Jan 21, 2011
Papers in SSE (vol 56, issue 1, february 2011)
Pages 13-17
Daolin Cai, Zhitang Song, Houpeng Chen, Xiaogang Chen
Research highlights
► Temperature model is constituted by an active region and a dispersed-heat region. ► Calculated and simulated the radius and crystalline fraction. ► Crystalline fraction and temperature increase with the reset voltage increasing.Microwave noise modeling of FinFETs Original Research Article
Pages 18-22
Giovanni Crupi, Alina Caddemi, Dominique M.M.-P. Schreurs, Wojciech Wiatr, Abdelkarim Mercha
Comprehensive numerical simulation of threshold-voltage transients in nitride memories Original Research Article
Pages 23-30
Aurelio Mauri, Salvatore M. Amoroso, Christian Monzio Compagnoni, Alessandro Maconi, Alessandro S. Spinelli
Research highlights
► We present a complete model to describe charge trap devices behavior. ► In this study any mathematical aspect regarding holes and electrons is detailed modeled. ► Experimental data coming from different TANOS and SONOS devices are correctly reproduced.A unified short-channel compact model for cylindrical surrounding-gate MOSFET Original Research Article
Pages 40-46
Bastien Cousin, Marina Reyboz, Olivier Rozeau, Marie-Anne Jaud, Thomas Ernst, Jalal Jomaah
Research highlights
► A compact model of short-channel effects for GAA MOSFET has been developed. ► The model uses a well-known extraction method making the model simple and accurate. ► Each term is used in a model core in order to provide a short-channel correction. ► The compact model is well described and is suitable with circuit design tools. ► The model is validated using TCAD simulations for all gate lengths down to 10nm.Physical limitations of the diffusive approximation in semiconductor device modeling Original Research Article
Pages 60-67
Tigran T. Mnatsakanov, Alexey G. Tandoev, Michael E. Levinshtein, Sergey N. Yurkov
Research highlights
► New criteria for occurrence of the diffusion mode were formulated. ► The applicability limits of the diffusion approximation in simulation were found. ► The analytical results are confirmed by a numerical experiment.Direct determination of threshold condition in DG-MOSFETs from the gm/ID curve Original Research Article
Pages 89-94
Ana Isabela Araújo Cunha, Marcelo Antonio Pavanello, Renan Doria Trevisoli, Carlos Galup-Montoro, Marcio Cherem Schneider
Dynamic model of AlGaN/GaN HFET for high voltage switching Original Research Article
Pages 135-140
Alexei Koudymov
A surface potential based drain current model for asymmetric double gate MOSFETs Original Research Article
Pages 148-154
Pradipta Dutta, Binit Syamal, N. Mohankumar, C.K. Sarkar
Research highlights
► We model a surface potential based drain current for asymmetric DG MOSFETs. ► The model is applicable for both heavily and lightly doped Silicon channel. ► The surface potential at both the gates are solved using proper Iterative techniques. ► The effect of volume inversion is shown in case of lightly doped channel.AlGaN/GaN hybrid MOS-HEMT analytical mobility model Original Research Article
Pages 201-206
A. Pérez-Tomás, A. Fontserè
Research highlights
► The hybrid normally-off switch AlGaN/GaN MOS-HEMT combines two main advantages: ► The MOS gate control and the high 2DEG mobility in AlGaN/GaN drift region. ► Here, we present simple analytical modeling of the on-resistance of a hybrid MOS-HEMT. ► We investigate the layout, the MOS channel mobility, the effect of a high-k and the temperature. ► The model can aid to understand the device physics and is compatible with TCAD simulation packages.Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction
Pages 214-218
J.C. Tinoco, A.G. Martinez-Lopez, J.-P. Raskin
Jan 20, 2011
[uSG] New Website
Daniel Oliveira (Microelectronics Students' Group)
Faculdade de Engenharia da Universidade do Porto
Rua Dr. Roberto Frias, s/n 4200-465 Porto PORTUGAL
mail: cmos@fe.up.pt, web: cmos.fe.up.pt
Jan 17, 2011
[mos-ak] 8th IWCM; Jan.25, 2011; Pacifico Yokohama, Japan
http://www.aspdac.com/aspdac2011/colocated_event/
January 25(Tue), 2011
Pacifico Yokohama room 419, Yokohama, Japan
The workshop provides an opportunity for the discussion and the
presentation of advances in modeling and simulation of integrated
circuits. Following IWCM sessions are foreseen:
Workshop Opening: M. Miura-Mattausch (chair)
Simulation Methodology (Chair: Z. Yu)
Conventional MOSFET (Chair: G. Yokomizo)
Organic Materials (Chair: W. Grabinski)
Power Device (Chair: Y. J. Park)
Closing: J. He (co-chair)
Complete IWCM program is available on-line:
http://home.hiroshima-u.ac.jp/usdl/IWCM/FILES/IWCM_Program_11_revised.pdf
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
Jan 12, 2011
[mos-ak] MOS-AK/GSA San Francisco Workshop Press Release
MOS-AK/GSA Modeling Working Group Holds Workshop in San Francisco
Experts Share Insight on Electron Device Modeling with Emphasis on
Simulation-Aware Models
can be found on the GSA site at: http://www.gsaglobal.org/news/article.asp?article=2011/0110
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To post to this group, send email to mos-ak@googlegroups.com.
To unsubscribe from this group, send email to mos-ak+unsubscribe@googlegroups.com.
For more options, visit this group at http://groups.google.com/group/mos-ak?hl=en.
Jan 10, 2011
Opprtunity with MNC Product Company in Bangalore
I copy a post from LinkedIn:
The member of technical staff (MTS) in this role will be responsible for the implementing and maintaining all device models for the company’s Analog FastSPICE (AFS) circuit simulator. The MTS will also debug various model-related circuit simulation issues such as convergence and accuracy issues, which will require working closely with circuit simulation developers and application engineers. The successful candidate will have sufficient circuit and circuit simulator background for these responsibilities.
Responsibilities
Implement and maintain all device models for the AFS circuit simulator.
Improve performance, convergence, and similar issues related to device models.
Verify device model accuracy and create testcases to validate and regression test accuracy.
Develop and maintain interfaces to implement models from Verilog-A and other simulators.
Lead AFS circuit simulator qualification for various foundry process technologies.
Work with applications and customers on select model and model interface development.
Requirements
3+ years experience in areas related to model development and circuit simulation.
Excellent knowledge of circuits containing diode, bipolar, and MOS devices.
Experience in debugging customer test cases for model and model related issues.
Good knowledge of Verilog-A and modeling in Verilog-A.
Outstanding programming skills in C/C++.
Excellent oral and written communication skills.
Ability work effectively within a worldwide development organization.
Masters or PhD degree in electrical engineering or relevant area.
Desirable
Familiarity with architecture of model implementation in true SPICE accurate simulators.
Previous experience in implementing device models in a circuit simulator.
Interested folks can contact bibin.sundaran at careernet.co.in, 9611833167