[paper] RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz

RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz
Jacopo Iannacci¹ and Christian Tschoban^2
1Center for Materials and Microsystems - CMM, Fondazione Bruno Kessler , Trento, ITALY
²Fraunhofer Institut für Zuverlässigkeit und Mikrointegration IZM , Berlin, GERMANY
Journal of Micromechanics and Microengineering
Accepted Manuscript online 8 February 2017

Abstract

RF-MEMS technology is indicated as a key enabling solution to realise the high-performance and highly-reconfigurable passive components that future 5G communication standards will demand for. In this work, we present, test and discuss a novel design concept of an 8-bit reconfigurable power attenuator manufactured in the RF-MEMS technology available at the CMM-FBK, in Italy. The device features electrostatically controlled MEMS ohmic switches, in order to select/deselect resistive loads (both in series and shunt configuration) that attenuate the RF signal, and comprises 8 cascaded stages (i.e. 8-bit), thus implementing 256 different network configurations. Fabricated samples are measured (S-parameters) from 10 MHz to 110 GHz in a wide range of different configurations, and modelled/simulated in Ansys HFSS. The device exhibits attenuation levels (S21) in the range from -10 dB to -60 dB, up to 110 GHz. In particular, the S21 shows flatness from 15 dB down to 3-5 dB, from 10 MHz to 50 GHz, while less linear traces up to 110 GHz. Comprehensive discussion is developed around the Voltage Standing Wave Ratio (VSWR), employed as quality indicator for the attenuation levels. Margins of improvement at design level are also discussed, in order to overcome the limitations of the presented RF-MEMS device. The results of S-parameter simulations performed in the Quite Universal Circuit Simulator (QUCS: qucs.sourceforge.net) for a few significant configurations of the RF-MEMS attenuator from 10MHz to 110GHz are reported, too. [read more...]

[SemiWiki] What are the future technology trend for SPICE Modeling?

CEO Interview: Albert Li of Platform Design Automation, Inc (PDA)

/Original material on SemiWiki/

by Daniel Nenni Published on 11-27-2016 02:00 PM

[SemiWiki] What are the future technology trend for SPICE Modeling?

[PDA] Having sufficient data is really the key to the problem, if data is sufficient, model can be automatically generated or synthesized. The concept has already been applied to the case of passive device modeling, such as modeling inductors. EM solvers play the role of proving more “data” or the synthesizers to generate models automatically. We’ve been working with the same concept for the active devices for quite a while, one way is to enable faster measurements, so that a lot more data can be collected and the other way is to achieve huge amount of data based on limited silicon through machine learning, which requires deep understanding of device behaviors, device modeling knowledge, data for the training and years of training experiences, we have already successfully applied the methodologies to our service projects, and tedious tasks such as model re-targeting is now purely done by machines. Machine Learning enabled model targeting from tweaking model parameters to just defining the targets and let the machine finish the job automatically

[SemiWiki] What are other areas in semiconductor you see that Machine Learning can help?

[PDA] We’ve published 3 papers in the past few years related to machine learning, and we used machine-learning algorithms to help on speeding up soft error simulation of logic circuits, automatic statistical modeling, and automatic RF front-end design,so the areas of machine-learning applications are massive. Algorithms, expertise, data and risk are the four key components to access Machine-Learning applications, take device characterization and modeling as examples, we have been working on the machine learning algorithms for over a decade, and we are definitely the experts in device characterization and modeling, we also have huge amount of data and models from previous projects, and these enabled us to train our software or instrument to achieve faster measurements and automatic model generations. 

[Book] Low-power HF Microelectronics: a unified approach

Low-power HF Microelectronics: a unified approach 

ISBN: 9780852968741 e-ISBN: 9781849193610

Editor: Gerson A. S. Machado

Department of Electronic Engineering

Imperial College of Science, Technology and Medicine

London, UK

Front Matter
1 Low-power HF microelectronics: a unified approach
Part 1: Process technology
2 Device structures and device simulation techniques
3 Stanford's ultra-low-power CMOS technology and applications
4 SOI technology
5 Radiation effects on ICs and a mixed analog CMOS-NPN-PJFET-on-insulator technology
Part 2: Device modelling/characterisation and circuit simulation
6 Modelling and characterisation of GaAs devices
7 The EKV Model: a MOST Model Dedicated to Low-Current and Low-Voltage Analogue Circuit Design and Simulation
8 Non-linear dynamic modelling of RF bipolar transistors
9 APLAC - object-oriented circuit simulator and design tool
10 Noise coupling in mixed-signal ASICs
Part 3: Reliability and test
11 Robust design and reliability analysis
12 Dynamic reliability of systems
13 Fault modelling and simulation for the test of integrated analog and mixed-signal circuits
Part 4: Circuit and system design methodology
14 High-speed and low-power techniques in CMOS and BiCMOS
15 Ultra-low-power digital design
16 Matched delay technique for high-speed digital design
17 Statistical design and optimisation for high-yield BiCMOS analog circuits
18 Design considerations for high-speed amplifiers using complementary BJTs
19 S2I techniques for analog sampled-data signal processing
20 Design of wireless portable systems
21 Low-power radio-frequency ICs and system architectures for portable communications
22 Analog and digital CMOS design for spread-spectrum wireless communications
23 Design considerations for BJT active mixers
24 Distortion in short channel FET circuits
25 Intelligent sensor systems and smart sensors: concepts, focus points and technology
26 Intelligent sensor systems and smart sensors: applications
Back Matter

[paper] Semiempirical Modeling of Reset Transitions in Unipolar, Resistive-Switching Based Memristors

Semiempirical Modeling of Reset Transitions in Unipolar Resistive-Switching Based Memristors

Rodrigo Picos, Juan Bautista Roldan, Mohamed Moner Al Chawa, Pedro Garcia-Fernandez, Francisco Jimenez-Molinos, Eugeni Garcia-Moreno 

Radioengineering, 24(2): 420-424 (2015)

We have measured the transition process from the high to low resistivity states, i.e., the reset process of resistive switching based memristors based on Ni/HfO2/Si-n+ structures, and have also developed an analytical model for their electrical characteristics. When the characteristic curves are plotted in the current-voltage (I-V) domain a high variability is observed. In spite of that, when the same curves are plotted in the charge-flux domain (Q-f), they can be described by a simple model containing only three parameters: the charge (Qrst) and the flux (frst) at the reset point, and an exponent, n, relating the charge and the flux before the reset transition. The three parameters can be easily extracted from the Q-f plots. There is a strong correlation between these three parameters, the origin of which is still under study [read more...]

Citation:    
Picos, R.; et al. Semiempirical Modeling of Reset Transitions in Unipolar Resistive-Switching Based Memristors; Radioengineering, 24(2): 420-424 (2015). [http://hdl.handle.net/10481/36994]

[paper] Statistical model of the NBTI-induced ΔVth, ΔSS, and Δgm degradations in advanced pFinFETs

Statistical model of the NBTI induced threshold voltage, subthreshold swing, and transconductance degradations in advanced pFinFETs
J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta
2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 15.3.1-15.3.4.
DOI: 10.1109/IEDM.2016.7838422

Abstract

We study the stochastic NBTI degradation of pFinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak g m improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of g m aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits. Selected nanoscale device characteristics resulting from 3 percolation paths, generated with the EKV model [read more...]

Publication stats: 1260 Reads

1260 Reads: Open-source circuit simulation tools for RF compact semiconductor device modelling

Article · Sep 2014 · International Journal of Numerical Modelling Electronic Networks Devices and Fields

[paper] Impact of technology scaling on analog and RF performance of SOI–TFET

Impact of technology scaling on analog and RF performance of SOI–TFET

P Kumari, S Dash and G P Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4 

Published 9 October 2015

Abstract

This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD Sentaurus device simulation results [read more...]

Citations
[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al  2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al  2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al  2015 447