Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic C-Inverters https://t.co/91uJURy3KA #papers

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic C-Inverters https://t.co/91uJURy3KA #papers

— Wladek Grabinski (@wladek60) October 25, 2016

from Twitter https://twitter.com/wladek60

October 25, 2016 at 09:07PM
via IFTTT

[ESSDERC Paper] Compact model for variability of low frequency noise due to number fluctuation effect

Compact model for variability of low frequency noise due to number fluctuation effect

N. Mavredakis and M. Bucher

2016 46th European Solid-State Device Research Conference (ESSDERC)

Lausanne, Switzerland, 2016, pp. 464-467

doi:10.1109/ESSDERC.2016.7599686

Abstract: Variability of low frequency noise (LFN) in MOSFETs is both geometry- and bias-dependent. RTS noise prevails in smaller devices where noise deviation is mostly area-dominated. As device dimensions increase, operating conditions determine noise variability maximizing it in weak inversion and increasing it with drain voltage. This dependence is shown to be directly related with fundamental carrier number fluctuation effect. A new bias- and area-dependent, physics-based, compact model for 1/f noise variability is proposed. The model exploits the log-normal behavior of LFN. The model is shown to give consistent results for average noise, variance, and standard deviation, covering bias-dependence and scaling over a large range of geometry.

Keywords: compact models, Low-frequency noise, MOSFET, Reactive power, Semiconductor device modeling, Shape, Standards, MOSFET, low frequency noise, noise variability

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7599686&isnumber=7598672

[SSE Paper] Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements

Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements 

Daniel Tomaszewski^a, Grzegorz Głuszko^a, Lidia Łukasiak^b,
Krzysztof Kucharski^a, Jolanta Malesinska^b

^aDivision of Silicon Microsystem and Nanostructure Technology, Instytut Technologii Elektronowej (ITE), ul. Okulickiego 5E, 05-500 Piaseczno, Poland 

^bInstitute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland

Abstract: An alternative method for an extraction of the MOSFET threshold voltage has been proposed. It is based on an analysis of the MOSFET source-bulk junction capacitance behavior as a function of the gate-source voltage. The effect of the channel current on the threshold voltage extraction is fully eliminated. For the threshold voltage and junction capacitance model parameters non-iterative methods have been used. The proposed method has been demonstrated using a series of MOS transistors manufactured using a standard CMOS technology.

Keywords: MOSFET CMOS Threshold voltage Junction capacitance Parameter extraction

Cite: Tomaszewski D et al. Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements. Solid State Electron (2016), http://dx.doi.org/10.1016/j.sse.2016.10.006

Sub-Minimum-Area MPW Sharing

Is Your Multi-Project Wafer Project Smaller Than the Fab Minimum Area?

Share the minimum area with other MPW customers to save mask costs

With the cost of mask sets going up with every node, even a multi-project wafer (MPW) can break your NRE budget, particularly if you plan to run multiple test spins. At 28nm, a 6mm2 area tile can cost over $100,000.

One solution is to share the minimum tile area with someone else who is using the same technology and metal stack that you are targeting. We periodically get these kinds of requests from customers. Please contact directly star@esilicon.com if you would like eSilicon to list your own MPW shuttle sharing opportunity, or if you would like eSilicon to contact you when future MPW tile sharing opportunities are available.

Following are upcoming opportunities to share a multi-project wafer (MPW) tapeout with another eSilicon customer. If you are interested, just email eSilicon.

Multi-Project Wafer Minimum Tile Sharing Opportunities for TSMC Technologies

Tapeout Month	Technology	Metal Stack	I/O	Price/mm2	Minimum Area	Final GDSII Due	Tapeout Date	Estimated Ship Date
October	65nm MS RF GP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	65nm MS RF LP	1P9M_6x1z1u	2.5V	$4,700	1mm2	October 10	October 12	November 23
	180nm MS RF G	1P6M_4x1u	3.3V	$1,000	5mm2	October 24	October 26	December 7
November	40nm MS RF LP	1P10M	1.8V	$7,500	1mm2	October 31	November 2	January 17

[read more...]

#Compact #Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime https://t.co/BsnCEEdo8a

#Compact #Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime https://t.co/BsnCEEdo8a

— Wladek Grabinski (@wladek60) October 21, 2016

from Twitter https://twitter.com/wladek60

October 21, 2016 at 04:54PM
via IFTTT

Free Semiconductor Books on SemiWiki

Download free PDF versions of three pivotal semiconductor books available on SemiWiki.com:

1. Mobile Unleashed: The History of ARM
2. Fabless: The Transformation of the Semiconductor Industry
3. EDAGraffiti: 25 years of experience in EDA

Only registered SemiWiki members can access these wiki pages so if you are not already a member please join as a guest: https://www.semiwiki.com/forum/register.php

[mos-ak] [2nd Announcement and Call for Papers] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

 9th International MOS-AK Workshop  

  Berkeley December 7, 2016 
    2nd Announcement and Call for Papers   

Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:

• Preannouncement - Sept 2016
• Call for Papers - Oct. 2016
• Final Workshop Program - Nov. 2016
• MOS-AK Workshop - Dec. 7 2016

Venue:

EECS Department
University of California, Berkeley

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies

Online MOS-AK Abstract Submission:
Prospective authors should submit online 

http://www.mos-ak.org/berkeley_2016/abstracts.php

(any related inquiries can be sent to abstracts@mos-ak.org)

Online Workshop Registration:

http://www.mos-ak.org/berkeley_2016/registration.php
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG19102016

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