[mos-ak] [Final Program] Spring MOS-AK Workshop Dresden March 18 2016

MOS-AK Workshop in DATE Conference Timeframe

Dresden, March 18 2016

The Final MOS-AK Workshop Program

Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, Extended MOS-AK TPC Committee as well as local organizers Martin Claus, CFAED, TU Dresden (D), Sandra Bley, CFAED, TU Dresden (D) and Alexander Petr, XFab, (D), we have pleasure to invite to the MOS-AK Workshop which will be held in Dresden on March 18, 2016. The MOS-AK workshop is organized with aims to strengthen an academic/industry network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue:   

Center for Advancing Electronics Dresden (CFAED)

Technische Universität Dresden

Würzburger Str. 46

01187 Dresden

Germany

Free Online Workshop Registration:

<http://www.mos-ak.org/dresden_2016/registration.php>

(any related inquiries can be sent to registration@mos-ak.org)

The Workshop Agenda and its Program is available online:

<http://www.mos-ak.org/dresden_2016/>

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special compact modeling issue of the International Journal of High Speed Electronics and Systems (IJHSES)

Extended MOS-AK Committee

WG10032016

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Numerical Analysis of Terahertz Emissions From an Ungated HEMT Using Full-Wave Hydrodynamic Model https://t.co/CJxKRangmP #papers #feedly

Numerical Analysis of Terahertz Emissions From an Ungated HEMT Using Full-Wave Hydrodynamic Model https://t.co/CJxKRangmP #papers #feedly

— Wladek Grabinski (@wladek60) March 4, 2016

from Twitter https://twitter.com/wladek60

March 04, 2016 at 08:49AM
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Adding Spice to Your Workbench https://t.co/TI79vLiaOO #todo #feedly #papers

Adding Spice to Your Workbench https://t.co/TI79vLiaOO #todo #feedly #papers

— Wladek Grabinski (@wladek60) February 27, 2016

from Twitter https://twitter.com/wladek60

February 27, 2016 at 11:41PM
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CMOS-SOI-MEMS Thermal Antenna and Sensor for Uncooled THz Imaging https://t.co/PiU56kluPf #papers #feedly

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— Wladek Grabinski (@wladek60) February 27, 2016

from Twitter https://twitter.com/wladek60

February 27, 2016 at 11:12PM
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Electrical Characterization of FDSOI by Capacitance Measurements in Gated p-i-n Diodes https://t.co/HtDcvhqiF1 #papers #feedly #papers

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— Wladek Grabinski (@wladek60) February 27, 2016

from Twitter https://twitter.com/wladek60

February 27, 2016 at 01:32PM
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An Experimental Demonstration of GaN CMOS Technology https://t.co/9Q50HGFkni #papers

An Experimental Demonstration of GaN CMOS Technology https://t.co/9Q50HGFkni #papers

— Wladek Grabinski (@wladek60) February 26, 2016

from Twitter https://twitter.com/wladek60

February 26, 2016 at 10:57PM
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Subthreshold Kink Effect Revisited and Optimized for Si Nanowire MOSFETs https://t.co/9Q50HGFkni #papers

Subthreshold Kink Effect Revisited and Optimized for Si Nanowire MOSFETs https://t.co/9Q50HGFkni #papers

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from Twitter https://twitter.com/wladek60

February 26, 2016 at 10:50PM
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Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching https://t.co/9Q50HGFkni #papers

Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching https://t.co/9Q50HGFkni #papers

— Wladek Grabinski (@wladek60) February 26, 2016

from Twitter https://twitter.com/wladek60

February 26, 2016 at 10:37PM
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Keysight: Full SPICE Characterization Flow

Keysight Technologies offers half a daya seminar at IEMN, Villeneuve d’Ascq. This free seminar is an opportunity to discover "Full SPICE Characterization Flow". The content is open, based on practical industrial and academic examples to illustrate the features of Keysight CAD/EDA software tools:

• Introduction (20 min)
• Part 1 - Measurements Automatization (30 min)
• Express WaferPro
• Part 2 - Spice Model Extraction  (60 min)
• IC-CAP
• MBP 
• Part 3 - Quality Assurance Model (20 mins)
• MQA 
• Q/A Session (20 min)

Place: Grand Amphithéâtre de l’IEMN, Laboratoire Centrale, Avenue Henri Poincaré F-59491 Villeneuve d’Ascq (F)
Date 17 March 2016

[Register online]

LibreCAD: Call for Your POTM Vote

The vote for April 2016 Community Choice SourceForge Project of the Month is now available, and will run until March 15, 2016 12:00 UTC. Here is one of the candidates:

LibreCAD is a fully comprehensive 2D CAD application that you can download and install for free. LibreCAD is an Open Source community-driven project: development is open to new talent and new ideas, and our software is tested and used daily by a large and devoted user community; you, too, can get involved and influence its future development. LibreCAD has GPLv2 public license – you can use it, customize it, hack it and copy it with free user support and developer support from our active worldwide community and our experienced developer team. There is a large base of satisfied LibreCAD users worldwide, and it is available in more than 20 languages and for all major operating systems, including Microsoft Windows, Mac OS X and Linux, including Debian, Ubuntu, Fedora, Mandriva, Suse, etc. 

Download LibreCAD now.

Alliance: FOSS VLSI/CAD System

Alliance is a complete set of free cad tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at SoC department of LIP6 laboratory of the Pierre & Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

Alliance VLSI CAD System is free software. Binaries, source code and cells libraries are freely available under the GNU General Public License (GPL). You are welcome to use the software package even for commercial designs without any fee. You are kindly requested to mention: "Designed with Alliance © LIP6, Université Pierre et Marie Curie".

ICs Designed with Alliance

• Smartlabs/Smarthome designed a complete circuit in the XFAB XH035 technology (2014).
• Tokai University (Shimizu Lab) designed the SNX, a 16 bits processor in the ROHM 0.18µm (2010).

Useful Links

• Improved Standard Cell libraries and documentation on how to design them, by Graham Petley: VLSI Technology
• A book presenting Alliance in depth: Introduction to VLSI CMOS Circuits design by Carlos SilvaCardenas, Takeo Yoshida & Alberto Palacios Pawlovsky.
• For Spanish readers, a set of tutorials made by Miguel Eduardo Flores Gomez from Don Bosco University: Tutorial de Alliance

[read more...]

[video] How to Model RF Passive Devices: Spiral Inductors

How to Model RF Passive Devices: Spiral Inductors

With increasing operating frequencies, the modeling of passive components becomes increasingly important, and there exist no ready-to-use models for inductors, resistors, capacitors etc. Based on the other video of this fundamental device modeling series, (How to Model RF Capacitors and Resistors), this video extends the topic to modeling RF Spiral Inductors. It explains how to develop a Spice model based on verified S-Parameter measurements. Applying an easy to follow, step by step procedure, the video walks you through the entire modeling flow for on-wafer inductors, using the Keysight Measurement and Modeling Software IC-CAP.

The IC-CAP project (modeling spiral inductors with and without metal-1 shielding) can be downloaded together with a detailed pdf explaining the steps demonstrated in the video.

To download the project files referred to in this video visit:
http://www.keysight.com/find/eesof-how-to-model-spiral-inductors

Published on Feb 11, 2016

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— Wladek Grabinski (@wladek60) February 18, 2016

from Twitter https://twitter.com/wladek60

February 18, 2016 at 07:59AM
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#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers

#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers

— Wladek Grabinski (@wladek60) February 10, 2016

from Twitter https://twitter.com/wladek60

February 10, 2016 at 12:46PM
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Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly

Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly

— Wladek Grabinski (@wladek60) February 10, 2016

from Twitter https://twitter.com/wladek60

February 10, 2016 at 07:57AM
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MIXDES 2016 Paper Submission Deadline

MIXDES Paper Submission Deadline
(March 1st, 2016)

---------- Forwarded message ----------
From: MIXDES 2016 Organizing Committee

Dear Colleagues,

I would like to kindly remind you that paper submission for MIXDES 2016 Conference has been already opened. The deadline for regular paper submission is March 1st, 2016, so I encourage you to register your papers. The instruction for paper preparation is available online. Please note that the paper format and content may be still updated up to Final Paper Version deadline (May 31st, 2016).

This year the MIXDES 2016 Conference will take place in Lodz, Poland, June 23-25, 2016. For more information regarding the conference please visit the MIXDES 2016 Conference web site at
www.mixdes.org.

If you have any questions please do not hesitate to contact me.

Hoping to see you in Lodz,

Mariusz Orlikowski
Secretary of the 23rd International Conference
"Mixed Design of Integrated Circuits and Systems"
MIXDES 2016
http://www.mixdes.org

Device to GDSII for IC Design Training

Hands on Training Program on “Device to GDSII for IC Design”

on 22-27 Feb 2016

Organized by VLSI Division of School of Electronics Engineering

Vellore Institute of Technology, Near Katpadi Rd Vellore, Tamil Nadu - 632014

The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap.

Target Audience: Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 40. 

Topics to ďe addressed:

Using TCAD:

• Structure Creation, Simulation and Device Simulation 
• Process Simulation 
• Multi-gate Transistors 
• Radiation study on devices and circuits

Using Cadence: 

• RTL Design and Simulation 
• Synthesis and low power synthesis Using RTL Compiler 
• Physical aware synthesis and DFT 
• Block and Top Level P&R Using SOC Encounter 
• STA Using Timing Engine 

[read more...]

Advanced Test Engineering Course

Barcelona, Spain

February 15-16, 2016 (2 days)

The course will highlight board and system-level manufacturing test and supportability issues. In order to achieve the unambiguous isolation of the faulty circuits, testability has to be assessed at the design stage – often before the circuit details are known. We will examine how this can be achieved using diagnostic assessment and modeling techniques. Finally, the course will evaluate the value of DFT and BIST at all levels of assembly from an economic perspective. You will leave the course with a thorough understanding of techniques, and guidelines you can put to use right away to manage automatic test and ATE at your company. The DFT and BIST methods will profit both manufacturing and support, while at the same time greatly improve the quality of units under test UUTs.

Who should attend: This course is not only of interest to designers and test engineers, but it will also be of great value to reliability, logistics, quality and manufacturing engineers. Managers concerned with testability and BIST techniques as part of DFX, as well as those with general interest of IEEE and military standards in DFT should find this course a great value.

Instructor: Louis Y. Ungar; Details and Availability [read more...]