#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers

#TFETs may #challenge MOSFETs https://t.co/9tyWFYJprp #cad #feedly #papers

— Wladek Grabinski (@wladek60) February 10, 2016

from Twitter https://twitter.com/wladek60

February 10, 2016 at 12:46PM
via IFTTT

Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly

Obama makes risky bid to increase #science #spending https://t.co/ckzMvs97eb #papers #feedly

— Wladek Grabinski (@wladek60) February 10, 2016

from Twitter https://twitter.com/wladek60

February 10, 2016 at 07:57AM
via IFTTT

MIXDES 2016 Paper Submission Deadline

MIXDES Paper Submission Deadline
(March 1st, 2016)

---------- Forwarded message ----------
From: MIXDES 2016 Organizing Committee

Dear Colleagues,

I would like to kindly remind you that paper submission for MIXDES 2016 Conference has been already opened. The deadline for regular paper submission is March 1st, 2016, so I encourage you to register your papers. The instruction for paper preparation is available online. Please note that the paper format and content may be still updated up to Final Paper Version deadline (May 31st, 2016).

This year the MIXDES 2016 Conference will take place in Lodz, Poland, June 23-25, 2016. For more information regarding the conference please visit the MIXDES 2016 Conference web site at
www.mixdes.org.

If you have any questions please do not hesitate to contact me.

Hoping to see you in Lodz,

Mariusz Orlikowski
Secretary of the 23rd International Conference
"Mixed Design of Integrated Circuits and Systems"
MIXDES 2016
http://www.mixdes.org

Device to GDSII for IC Design Training

Hands on Training Program on “Device to GDSII for IC Design”

on 22-27 Feb 2016

Organized by VLSI Division of School of Electronics Engineering

Vellore Institute of Technology, Near Katpadi Rd Vellore, Tamil Nadu - 632014

The relentless march fast of the CMOS has slowed down and the semiconductor industry is looking for novel and innovative devices. Many novel devices are being explored currently. TCAD and Cadence tool allows us to generate new structures, circuits and analyze its performance. Unlike other circuit simulators, TCAD and Cadence needs a special training. This hands on training addresses this gap.

Target Audience: Faculty, students and research scholars from various engineering colleges of India. The number of participants is limited to 40. 

Topics to ďe addressed:

Using TCAD:

• Structure Creation, Simulation and Device Simulation 
• Process Simulation 
• Multi-gate Transistors 
• Radiation study on devices and circuits

Using Cadence: 

• RTL Design and Simulation 
• Synthesis and low power synthesis Using RTL Compiler 
• Physical aware synthesis and DFT 
• Block and Top Level P&R Using SOC Encounter 
• STA Using Timing Engine 

[read more...]

Advanced Test Engineering Course

Barcelona, Spain

February 15-16, 2016 (2 days)

The course will highlight board and system-level manufacturing test and supportability issues. In order to achieve the unambiguous isolation of the faulty circuits, testability has to be assessed at the design stage – often before the circuit details are known. We will examine how this can be achieved using diagnostic assessment and modeling techniques. Finally, the course will evaluate the value of DFT and BIST at all levels of assembly from an economic perspective. You will leave the course with a thorough understanding of techniques, and guidelines you can put to use right away to manage automatic test and ATE at your company. The DFT and BIST methods will profit both manufacturing and support, while at the same time greatly improve the quality of units under test UUTs.

Who should attend: This course is not only of interest to designers and test engineers, but it will also be of great value to reliability, logistics, quality and manufacturing engineers. Managers concerned with testability and BIST techniques as part of DFX, as well as those with general interest of IEEE and military standards in DFT should find this course a great value.

Instructor: Louis Y. Ungar; Details and Availability [read more...]

Simulating the World’s Smallest Integrated Switch

This visualization from CSCS in Switzerland shows the world’s smallest integrated switch.

The switch is based on the voltage-induced displacement of one or more silver atoms in the narrow gap between a silver and a platinum plate.

Researchers working under Juerg Leuthold, Professor of Photonics and Communications at ETH Zurich, have created the world’s smallest integrated optical switch. Applying a small voltage causes an atom to relocate, turning the switch on or off. ETH Professor Mathieu Luisier, who participated in this study, simulated the system using Piz Daint Supercomputer. The component operates at the level of individual atoms. The team’s latest development was recently presented in the journal Nano Letters.

gEDA Edinburgh meetup - Saturday 6th February 2016

gEDA Edinburgh Meetup

Saturday 6th February 2016

---------- Fwd message ----------
From: "Peter TB Brett"
Date: 3 Feb 2016 13:57
Subject: gEDA Edinburgh meetup - Saturday 6th February 2016 
----------

Hi all,
There will be a UK meet-up and hack day this weekend.

• Edinburgh, UK
  Saturday 6th of February

It'll be at my place, so if you want to come, send me a direct e-mail and I'll send details by private e-mail.

Sorry for the short notice. It's on Saturday so as not to conflict with the PCB hack day on Sunday.

Peter Clifton and I will both be there, and everybody else who can attend for all or some of the day will be welcome. We'll also be using the #geda channel on irc.oftc.net

If you use or develop free and open source system (FOSS) design and simulation software, you'd be welcome to attend!

Peter

---------- End of Fwd message ----------