Jun 17, 2010

An interesting (educative?) post in EDN by Paul Rako :

Op-amp Spice macro-models article from Intersil

June 16, 2010
Former EDN analog editor Bill Schweber has published a good article from Tamara Schmitz and Jian Wong about developing Spice macromodels for voltage-feedback op-amps. Part 1 (pdf), and part 2 (pdf). All the youngsters like to use Spice for op-amp circuit design but I am more like Bob Pease and Jim Williams, you have to build the circuit to know what is going on. I will never forget being perfectly happy with a Spice run, until I built the circuit and realized that the quad op amp was running way too hot. I did not notice the power consumption of each of the amps was about ¼ W. That was a newbee mistake, sure, but even if Spice does not lie, it is the product of digital and software minds, so rather than flashing a big red sign that warns you that you are going to burn up the quad op amp, they just require you to define a power variable and display it and then print the result in the same tiny test and the blizzard of other information. Then software people smile and fold their arms and tell us everything is our fault, since the information was right there if only we asked for it.  The one thing about analog is that is has a sense of importance. That’s why steering wheels and shift levers are big and prominent and radio treble controls are tiny little buttons. If software people designed cars everything would be a tiny little icon and the crash warnings would be in 10-point text.
So anyway, Spice does not necessarily lie like Bob Pease says, but I guarantee you that if you give it poor models it will give you the wrong answer. This is the big hassle with op amp models. Some of them, like the old National Semi Comlinear models (pdf) published by Mike Steffes before he left for Burr Brown and now Intersil were essentially transistor-level models. An IC designer could infer the design of the part from them. Mike told me that he knew that, but it was just so important to give an accurate model that he felt he had to release those great models. If someone wanted to copy the circuits, well, they had a lot more work to do-anyone can de-cap an op amp and reverse engineer it in a day. That still does not give you the process or the testing regime or the design secrets and tricks.
That is why this Intersil article is so important. Anything that helps you make good models is important in a world where kid engineers trust a computer rather than a breadboard. The article give some history of op amp models and that will tip you off as to what you can expect from a simulation. If the model you use does not model for 1/f noise, and most vendor models do not, you cannot get a meaningful simulation of low-frequency noise performance of the circuit. If the model does include flat-band noise and you are designing and ac-coupled video circuit, well that is fine for your needs. I have yet to see a Spice op-amp model that accurately tells you what happens if you bang the output into the rails and saturate the transistors. I will ask Mike Steffes if his old Comlinear models would do that, and leave a comment.

Jun 15, 2010

Modeling The Bipolar Transistor (Book)

Modeling The Bipolar Transistor (*)
By Ian Getreu
(2009; Paperback, 286 pages)

The book describes the bipolar transistor model and parameter measurement techniques for the SPICE circuit simulator. Originally published by Tektronix in 1974, this is a slightly modified revision republished in 2009 by the original author.

Read the review by Colin McAndrew

(*) There is a $4.00 discount if people order it by June 30 - use the coupon code: SUMMERREAD305.

Jun 11, 2010

IEEE Awards 2010


Takayasu Sakurai, has got the 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, for pioneering contributions to the design and modeling of high-speed and low-power CMOS logic circuits.



Note that this is not compact modeling, but his alpha power law model has had a big impact!


Gennady Gildenblat has got promoted to IEEE Fellow for his "contributions to modeling of metal-oxide semiconductor field effect transistors".

Yasuhisa Omura has got promoted to IEEE Fellow for the contributions made to the SOI technology, analysis and modelling.

Thomas Piotr Skotnicki also got the promotion to IEEE Fellow for contributing to the development of MOS models.



Congratulations to all of them!

Jun 8, 2010

Physicists from Mainz University develop a quantum interface between light and atoms



Ultra-thin glass fiber enables the controlled coupling of light and matter / publication in Physical Review Letters:

E. Vetsch, D. Reitz, G. Sagué, R. Schmidt, S. T. Dawkins, and A. Rauschenbeutel
Optical interface created by laser-cooled atoms trapped in the evanescent field surround-ing an optical nanofiber
Physical Review Letters, May 21, 2010
DOI: 10.1103/PhysRevLett.104.203603

Jun 7, 2010

2010 IEDM CALL FOR PAPERS

Submission Deadline is June 25, 2010!

The IEEE International Electron Devices Meeting is the Annual Technical Meeting of the Electron Devices Society.  This year it will be held at the Hilton San Francisco Union Square, San Francisco, CA USA December 6-8, 2010.

Increased participation in the areas of energy harvesting, power devices, biomedical devices and circuit-technology interaction is desired.

Information about IEDM can be found at: http://www.ieee-iedm.org

Social Networking: 
Twitter: http://twitter.com/ieee_iedm
 
Facebook:
http://www.facebook.com/search/?q=IEDM&init=quick#/pages/IEDM/131119756449?ref=search&sid=6112806.762392748..1



MEETING HIGHLIGHTS 
 * Three plenary presentations by prominent experts. 
 * Invited papers on all aspects of advanced devices and technologies. 
 * An Emerging Technology session. 
 * Panel discussion.
 * Presentation of IEEE/EDS awards. 
 * IEDM Luncheon presentation will be held on Tuesday, December 7.
 * Two short courses will be held on Sunday December 5.

Abstract Submission
 * Web-based submission of abstracts (http://www.ieee-iedm.org)
 * Deadline for submissions is June 25, 2010 

For further information on submissions, go to http://www.ieee-iedm.org and click on call for papers.  Download the pdf of the call for papers with more detailed information.

Questions/Comments, contact the IEDM Conference office at:
phyllism@widerkehr.com or 301-527-0900 ext. 2

Jun 3, 2010

Training Course on Compact Modeling: Final Programme

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

I want to remark that ON JUNE 30 AND JULY 1 THERE ARE NO SOCCER WORLD CUP MATCHES.

So, participants do not have to worry to miss soccer matches during the duration of the Training Course!


The final programme, with the timetable, is already available:


Day 1: June 30, 2010 (Wednesday)
8:15
Training Courses Opening
Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
8:30
Statistical variability and corresponding compact model strategies
Asen Asenov (University of Glasgow)
9:45
Electrical characterization of SOI and Multi-Gate MOSFETs
Sorin Cristoloveanu (MINATEC and LETI, France)
11:00
Coffee Break
11:30
Transport modeling
Tibor Grasser (TU-Wien, Austria)
12:45
Analytical 2D and 3D electrostatic modeling
Tor A Fjeldly (UniK, Norway)
14:15
Lunch
15:15
Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs
Kiyoo Itoh (Hitachi, Japan)
16:30
GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization
Wladek Grabinski
20:30
Gala Dinner






Day 2: July 1, 2010 (Thursday)
8:30
Analytical small-signal modeling
Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
9:45
DC Parameter Extraction
Antonio Cerdeira (Cinvestav, Mexico)
11:00
Coffee Break
11:30
Compact, High Frequency Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET
Ilcho Angelov (Chalmers University, Sweden)
12:45
Noise modeling
Jamal Deen (McMaster University, Canada)
14:15
Lunch
15:15
Electro-thermal and reliability modeling
Renaud Gillon (On Semiconductor, Belgium)
16:30
Leakage power modeling for the reduction of power consumption in CMOS ICs
Massimo Poncino (Politecnico di Torino, Italia)
17:45
Training Courses Closing

And nice weather is usual in Tarragona at the end of June/beginning of July. Participants who spend a few more days in Tarragona can enjoy the nice beaches around, or doing sightseeing in the Tarragona area, Barcelona (only 100 Km far from Tarragona) and other places in Catalonia.

Tarragona is well connected to Barcelona by rail and highway. There are direct buses from Barcelona Airport. Besides, there are direct flights to Reus Airport (less than 15 Km far from Tarragona) from many European cities by Ryanair.

STM confirms 20nm by end of 2012

The chief technology officer at STMicroelectronics, Jean-Marc Chery, today confirmed at the Field Trip conference in London that its first 20nm process will be going into production at its French fab by Q4 2012. [more]

Intel's timbers could be shivered. In Q1 2010 alone ST had revenue of $2,323 million USD and it was the #1 EMEA semiconductor company in 2009.

Jun 2, 2010

Toshiba Invention Brings Quantum Computing Closer

Quantum computers are likely to be used initially to solve problems that are otherwise virtually intractable, such as modeling new molecules in pharmaceuticals. The Toshiba team, working with the University of Cambridge's Cavendish Laboratory, described their invention in a paper in the journal Nature.

Technorati Tags:

Jun 1, 2010

Fastest Integrated Circuit Doubles the Previous Record, Getting Close to One Terahertz


The 670 GHz compact circuit layout (right), alongside a detail of Northrop Grumman's 30-nanometer Indium Phosphide T-gate (left). Northrop Grumman [more]

May 30, 2010

NHK Improves Resolution of Organic TFT-driven OLED Panel

NHK Science & Technology Research Laboratories (STRL) exhibited a flexible OLED panel driven by organic TFTs at OpenHouse 2010, which took place from May 27 to 30, 2010, in Tokyo [more]

May 27, 2010

[mos-ak] C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville on Sept. 17, 2010


You received this message because you are subscribed to the Google Groups "mos-ak" group.
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C4P MOS-AK/GSA ESSDERC/ESSCIRC Workshop:  http://www.mos-ak.org/seville/
"Frontiers of the Compact Modeling for Advanced Analog/RF Applications"

The MOS-AK/GSA Workshop in Seville will be organized as an integral
part of the ESSDERC/ESSCIRC Conference. The MOS-AK/GSA Workshop is
HiTech forum to discuss the frontiers of the electron devices modeling
with emphasis on simulation-aware models. Original papers presenting
new developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
   * Compact Modeling (CM) of the electron devices
   * Verilog-A language for CM standardization
   * New CM techniques and extraction software
   * CM of passive, active, sensors and actuators
   * Emerging Devices, CMOS and SOI-based memory cells
   * Microwave, RF device modeling, high voltage device modeling
   * Nanoscale CMOS devices and circuits
   * Technology R&D, DFY, DFT and IC Designs
   * Foundry/Fabless Interface Strategies

On-line abstract submission is open with the deadline on July 15, 2010.

Further details and updates: http://www.mos-ak.org/seville/

==========================================================
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Tarragona: June.31-July.1  http://www.compactmodelling.eu/tc_programme.php
* Seville: Sept. 17  http://www.mos-ak.org/seville/
* California: Dec'2010 http://www.mos-ak.org/
==========================================================
You received this message because you are subscribed to the Google Groups "mos-ak" group.
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May 26, 2010

IEEE papers in May 2010

Why the Universal Mobility Is Not

Cristoloveanu, S.  Rodriguez, N.  Gamiz, F. 
Digital Object Identifier : 10.1109/TED.2010.2046109
Examples taken from ultrathin silicon-on-insulator (SOI) transistors tend to contradict the universality of mobility-field dependence. We revisit the meaning of the effective field concept and its implications on the universal mobility curve (UMC). Poisson–Schroedinger simulations point out the inappropriateness of the standard definitions of effective field when dealing with SOI or double-gate devices. Different carrier distributions can lead to the same value of the effective fie... Read More »

Compact and Distributed Modeling of Cryogenic Bulk MOSFET Operation

Akturk, A.  Holloway, M.  Potbhare, S.  Gundlach, D.  Li, B.  Goldsman, N.  Peckerar, M.  Cheung, K. P. 
Digital Object Identifier : 10.1109/TED.2010.2046458

We have developed compact and physics-based distributed numerical models for cryogenic bulk MOSFET operation down to 20 K to advance simulation and first-pass design of device and circuit operation at low temperatures. To achieve this, we measured and simulated temperature-dependent current–voltage characteristics of 0.16- and 0.18-$muhbox{m}$ bulk MOSFETs. Our measurements indicate that these MOSFETs supply approxim... Read More »


Compact Modeling of Experimental n- and p-Channel FinFETs

Song, J.  Yuan, Y.  Yu, B.  Xiong, W.  Taur, Y. 
Digital Object Identifier : 10.1109/TED.2010.2047067

The analytic potential model for symmetric double-gate MOSFETs is verified and calibrated with experimental n- and p-channel FinFET data over a wide range of gate lengths and bias regions. Quantum mechanical effects are incorporated in the model to reproduce the measured $C$$V$ characteristics. The long-channel mobility consists of both a phonon scat... Read More »

Compact Modeling of a Magnetic Tunnel Junction—Part I: Dynamic Magnetization Model

Kammerer, J.-B.  Madec, M.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047070

The potential application range of spintronic devices is wide. However, few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: the first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part, a... Read More »



Compact Modeling of a Magnetic Tunnel Junction—Part II: Tunneling Current Model

Madec, M.  Kammerer, J.-B.  Hébrard, L. 
Digital Object Identifier : 10.1109/TED.2010.2047071

The potential application range of spintronic devices is wide. However, a few works were carried out in the field of compact modeling of such devices. The lack of compact models dramatically increases the design complexity of circuits using spintronic devices. In this paper, focus is made on magnetic tunnel junctions (MTJs). It is presented in a set of two papers: The first part deals with the magnetic aspects of the MTJ, whereas the second one covers the electrical aspects. In this part,... Read More »



Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design

Kashyap, A. S.  Mantooth, H. A.  Vo, T. A.  Mojarradi, M. 
Digital Object Identifier : 10.1109/TED.2010.2046073

The cryogenic characterization (93 K/$- hbox{180} ^{circ}hbox{C}$ to 300 K/27 $^{circ}hbox{C}$) and compact modeling of a high-voltage (HV) laterally diffused MOS (LDMOS) transistor that exhibits carrier freeze-out are presented in this paper. Unlike low-voltage MOS devices, it was observed that HVMOS structures experience freeze-out effects at much higher t... Read More »



Variability Analysis of TiN Metal-Gate FinFETs

Endo, K.  O'uchi, S.  Ishikawa, Y.  Liu, Y.  Matsukawa, T.  Sakamoto, K.  Tsukada, J.  Yamauchi, H.  Masahara, M. 
Digital Object Identifier : 10.1109/LED.2010.2047091

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the $V_{rm th}$ in the FinFET occurs and the standard deviations of the $V_{rm th}$ of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the $V_{rm th}$ var... Read More »

Transistor mismatch in 32 nm high-k metal-gate process



 

Extraction Technique of Trap Densities in Thin Films and at Insulator Interfaces of Thin-Film Transistors

Kimura, M. 
Digital Object Identifier : 10.1109/LED.2010.2045221

We have developed an extraction technique of trap densities in thin films and at insulator interfaces of thin-film transistors (TFTs). These trap densities can be extracted and separated from capacitance–voltage and current–voltage characteristics by numerically calculating $Q = CV$ , Poisson equation, carrier density equations, and Gauss' law. The outstanding advantages are intuitive understandability and a s... Read More »









May 18, 2010

Some papers (May 2010) I've found interesting...

Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors

Bronckers, S.;   Van der Plas, G.;   Vandersteen, G.;   Rolain, Y.;  
Interuniversity Microelectronics Centre (IMEC), Leuven, Belgium 
This paper appears in: Instrumentation and Measurement, IEEE Transactions on
Issue Date: June 2010
Volume:
59 Issue:6
On page(s): 1727 - 1733
ISSN: 0018-9456
Digital Object Identifier: 10.1109/TIM.2009.2024370 
Date of Publication: 03 May 2010
Date of Current Version: 10 May 2010

Substrate noise issues are a showstopper for the smooth integration of analog and digital circuitries on the same die. For the designer, it is not known how substrate noise couples into the transistors of the analog circuitry. This paper reveals the dominant coupling mechanisms with simulations and the corresponding measurements in a 0.13-$muhbox{m}$ triple-well common-source complementary metal–oxide–semiconductor (CMOS) transistor integrated on a lightly doped substrate. Substrate noise couples in either the ground or the bulk of the transistor. It is demonstrated that the importance of the coupling mechanisms depends on the resistance of the ground interconnect. For the technology node used, measurements show that substrate noise isolation is optimal for a ground resistance of 0.8 $Omega$.


Thermal shot noise in top-gated single carbon nanotube field effect transistors

Chaste, J.;   Pallecchi, E.;   Morfin, P.;   Feve, G.;   Kontos, T.;   Berroir, J.-M.;   Hakonen, P.;   Placais, B.;  
Laboratoire Pierre Aigrain, Ecole Normale Supérieure, CNRS (UMR 8551), Université P. et M. Curie, Université D. Diderot, 24, rue Lhomond, 75231 Paris Cedex 05, France 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume:
96 Issue:19
On page(s): 192103 - 192103-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3425889 
Date of Current Version: 13 May 2010


The high-frequency transconductance and current noise of top-gated single carbon nanotube transistors have been measured and used to investigate hot electron effects in one-dimensional transistors. Results are in good agreement with a theory of one-dimensional nanotransistor. In particular the prediction of a large transconductance correction to the Johnson–Nyquist thermal noise formula is confirmed experimentally. Experiment shows that nanotube transistors can be used as fast charge detectors for quantum coherent electronics with a resolution of
13 μe/
 Hz

in the 0.2–0.8 GHz band. 

Dielectric constants of atomically thin silicon channels with double gate

Kageshima, Hiroyuki;   Fujiwara, Akira;  
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193102 - 193102-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427364 
Date of Current Version: 13 May 2010
Dielectric constants of Si (111) nanofilms with the double gate are studied in the full inversion regime by using the first-principles calculation. The calculations show that the dielectric constants are significantly smaller than that of the bulk. Further, the dielectric constants depend on the conduction type as well as on the film thickness. They also oscillate with a 2-bilayer-thickness for the p-channel case as the film thickness decreases. The suppressed dielectric constants are found in the channel center as well as in the channel surface. These findings open the way to artificial control of the dielectric constant in semiconductor nanostructures.
 

Charge carrier densities in chemically doped organic semiconductors verified by two independent techniques

Lehnhardt, M.;   Hamwi, S.;   Hoping, M.;   Reinker, J.;   Riedl, T.;   Kowalsky, W.;  
Institute for High-Frequency Technology, Technical University of Braunschweig, Schleinitzstr. 22, D-38106 Braunschweig, Germany 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume: 96 Issue:19
On page(s): 193301 - 193301-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3427416 
Date of Current Version: 13 May 2010

The charge carrier density of the p-type doped organic semiconductor 2,7-bis(9-carbazolyl)-9,9-spirobifluorene is determined for varied doping concentrations. As p-type dopant molybdenum trioxide is used. We determine the carrier density by measuring the polaron induced optical absorption and by a capacitance-voltage analysis. We show that both results are in excellent agreement. An almost linear dependence of the charge carrier density on the doping concentration is observed. Carrier densities on the order of 1018 cm-3 at a dopant concentration of 1 mol % can be achieved. Overall, a low doping efficiency on the order of 2%–4.5% is evidenced.


The effect of traps on the performance of graphene field-effect transistors

Zhu, J.;   Jhaveri, R.;   Woo, J. C. S.;  
Department of Electrical Engineering, University of California–Los Angeles, Los Angeles, California 90095-1594, USA 
This paper appears in: Applied Physics Letters
Issue Date: May 2010
Volume:
96 Issue:19
On page(s): 193503 - 193503-3
ISSN: 0003-6951
Digital Object Identifier: 10.1063/1.3428785 
Date of Current Version: 13 May 2010

This paper studies the performance degradation of graphene field-effect transistors due to the presence of traps. The mobile charge modulation by gate voltage is degraded because of immobile trapped charges. As a result the current is reduced and the on/off ratio is decreased. Extracted mobility using transconductance method is shown to be underestimated considerably due to the effect of traps.
 

May 11, 2010

Training Course on Compact Modeling: Registration Open

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona, Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

The lectures and topics of their lectures will be the following:


1. Tibor Grasser (TU-Wien, Austria) - Transport modeling

2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling

3. Jamal Deen (McMaster University, Canada) - Noise modeling

4. Benjamin Iñiguez (URV, Spain) - Analytical small-signal modeling

5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling

6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling

7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs

8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies

9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"

10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"

11. Antonio Cerdeira (Cinvestav, Mexico) - "DC Parameter Extraction"

12. Massimo Poncino (Politecnico di Torino, Italia) - "Leakage power modeling for the reduction of power consumption in CMOS ICs"

The final programme, with the timetable, is already available!

May 8, 2010

May 7, 1952: The Integrated Circuit …



1952: British radar engineer Geoffrey Dummer introduces the concept of the integrated circuit at a tech conference in the United States. The world is about to change. Read more... by www.wired.com

Organic Transistor Could Outshine OLEDs



”The light-emitting transistor is a remarkably versatile device architecture,” says Alan Heeger, a physics professor at the University of California, Santa Barbara. Heeger’s lab developed an OLET inverter circuit earlier, but its quantum efficiency was much lower. He called the 5 percent external quantum efficiency ”remarkable,” because it suggests that nearly 100 percent of the carriers in the emissive layer are emitting photons. ”If that is indeed true,” Heeger says, ”they have made an important step forward.”

May 7, 2010

3rd International Workshop on Copact TFT Modeling for Circuit Simulation: Deadline Extended

The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.

Deadline for abstract submission has been extended:

- Deadline for abstract submission: May 19, 2010
- Notification of acceptance: May 26, 2010
- Camera-ready version: Jun 18, 2010

The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.

Topics:
A partial list of the areas of interest includes:

- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels

Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat



This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

May 5, 2010

EPFL MicroNano Fabrication Annual Review Meeting

The Networking Event organized by the EPFL Center of MicroNanoTechnology (CMi)

Date: Tuesday May 18th, 2010
Time: 09h30 - 17h00
Place: EPFL Lausanne, Salle Polyvalente, Centre Est, CE 1 515

Program :
The presented topics include:
  • Biomedical Applications (Microfluidics, Cellular-Manipulation, Microelectrode Arrays, Molecules Detection, BioMicroNanoSystems, ...)
  • Optics (Nanophotonics, Optomechanics, Optofluidics, MOEMS, ...)
  • Micro and Nanoelectronics (Nanowires, High-Q Resonators, RF MEMS and Switches, 3D integration, CMOS, ...)
  • Nanostructure Physics (III/V Devices, Nanotubes, Nanowires, Nanomechanics, ...)
  • Material Sciences (Graphene, Polymers, Piezoelectric Ceramics, Photovoltaic Materials, Micro Fuel Cells, ...)
  • MEMS, NEMS (Motors, Tweezers, Sensors and Actuators, Micro and Nanomechanics, ...)
  • Micro and Nanofabrication Technologies (Self-Assembly, EBEAM Lithography, Dry Etching, Thin Films, Photolithography, FIB, CMP, ...)
  • Packaging and Assembly
Registration is required by sending an email to: claudia.dagostino@epfl.ch

May 3, 2010

[mos-ak] MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville: 1st announcement

MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Seville
*** 1st announcement ***

Date: September 17, 2010
Venue: Barceló Hotel Renacimiento

Co-Located With:
* 40th European Solid-State Device Research Conference (ESSDERC):
http://www.essderc2010.org
* 36th European Solid-State Circuits Conference (ESSCIRC) :
http://www.esscirc2010.org
* CMC Meeting (Q3 Event in Madrid): http://www.geia.org/index.asp?bid=597

More MOS-AK/GSA information and updates: http://www.mos-ak.org/seville/

Extended MOS-AK/GSA Committee:
===========================
http://www.mos-ak.org/committee.html
===========================
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster

MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil

MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Sebastian Schmidt, XFab
Co-Chair: Prof. Benjamin Iniguez, URV

MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
===========================

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May 2, 2010

Thoughts on Directions for Silicon Technology Development as we Approach the End of CMOS Scaling

Speaker: Dr. Tak H. Ning, IBM and IEEE Fellow, and co-author of the Taur & Ning textbook now in its second edition.
Date: TUESDAY, May 11, 2010; Time: 6:00 PM - Pizza, 6:15 PM – Lecture; Cost: Free
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051
Web link: http://www.ewh.ieee.org/r6/scv/eds/
Contact: Sandeep Bahl

Apr 29, 2010

POWER/HVMOS Devices Compact Modeling

POWER/HVMOS Devices Compact Modeling
W. Grabinski and T. Gneiting, (Eds.)
1st Edition., 2010, V, 300 p., Hardcover
ISBN: 978-90-481-3045-0

Content Level » Research

Keywords » HV EKV, HV HiSIM,MM20, compact modeling - LDMOS, VDMOS, quasi-saturation, self heating - power, high voltage semiconductor devices




TABLE OF CONTENTS
CHAPTER 1: Numerical Power/HV Device Simulations; Oliver Triebl and Tibor Grasser.

CHAPTER 2: HiSIM-HV: A scalable, surface-potential-based compact model for symmetric and asymmetric high-voltage MOSFETs; Hans J. Mattausch, Norio Sadachika, M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch.

CHAPTER 3: MM20 HVMOS Model: a surface-potential based LDMOS model for circuit simulation; Annemarie Aarts and Alireza Tajic.

CHAPTER 4: Practical HV DMOS modeling using HVEKV; Yogesh Singh Chauhan, Francois Krummenacher and Adrian Mihai Ionescu.

CHAPTER 5: Power Devices; Andrzej Napieralski, Malgorzata Napieralska and Lukasz Starzak.

CHAPTER 6: Distributed modeling approach applied to the IGBT; Patrick Austin and Jean-Louis Sanchez.

CHAPTER 7: Web Based Modeling Tools; Andrzej Napieralski, Lukasz Starzak, Bartlomiej Swiercz and Mariusz Zubert.

Apr 27, 2010

[mos-ak] MOS-AK/GSA Rome Workshop Press Release

MOS-AK/GSA Modeling Working Group Holds Workshop in Rome
Academic and Industrial Experts Share Their Latest Perspectives on
Compact Modeling and Verilog-A Standardization
http://www.gsaglobal.org/news/article.asp?article=2010/0426

in other sources:

http://www.marketwatch.com/story/mos-akgsa-modeling-working-group-holds-workshop-in-rome-2010-04-26?reflink=MW_news_stmp
http://ca.news.finance.yahoo.com/s/26042010/34/biz-f-business-wire-mos-ak-gsa-modeling-working-group-holds-workshop.html
http://www.forbes.com/feeds/businesswire/2010/04/26/businesswire138742381.html
http://www.finanznachrichten.de/nachrichten-2010-04/16725421-mos-ak-gsa-modeling-working-group-holds-workshop-in-rome-004.htm
http://it.tmcnet.com/news/2010/04/26/4750513.htm

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New IEEE EDS Senior Members

My warmest welcome to the new IEEE Senior Members of the EDS in April:

Alberto Adan, Carlos Araujo, M Scott Burroughs, Gerd Hechtfischer, Aaron Ho, Syed Islam, Ioannis Kymissis, Sungjae Lee, Xian Liu, M Madheswaran, Enrique Miranda, Michael Parker, Vijay Reddy, Sean Rommel, Nikita Ryskin, Nayanathara Sattiraju, Keyhan Sinai, Bhaskar Srinivasan, Munehiro Tada, Tsuyoshi Tanaka, Thy Tran, Mingwei Xu, Tetsuo Yamada

Apr 23, 2010

[mos-ak] MOS-AK/GSA Rome workshop on-line publications

MOS-AK/GSA Rome workshop on-line publications are available:
http://www.mos-ak.org/rome/

I would like to thank all MOS-AK speakers and poster presenters for
sharing their compact modeling competence, R&D experience and
delivering valuable MOS-AK presentations. I am sure, that our modeling
event in Rome was beneficial to all MOS-AK Workshop attendees.

Organization of our modeling event would not be possible without our
generous sponsor: Agilent Technologies, Micron and Micron Foundation
as well as the IEEE EDS, technical co-sponsor. I also would like to
personally acknowledge local organizers, in particular, Professors
Fernanda Irrera and Marco Balucani for their dedication, commitment.
My very special 'thank you' goes to Angela Gatto and Paolo Nenzi not
only for providing smooth workshop logistics.

I hope, we would have a next chance to meet all of you and your
academic and industrial partners at future MOS-AK/GSA modeling events
(listed below).

-- with regards - WG (for the MOS-AK/GSA)
==========================================================
* London: May 18-19, www.gsaglobal.org
* Tarragona: Jun.30-Jul.1 www.compactmodelling.eu/an_details.php?anID=14
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Seville: Sept. 17 www.mos-ak.org/seville http://www.essderc2010.org/
* San Francisco: Dec'10 www.mos-ak.org
==========================================================

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Apr 20, 2010

3rd International Workshop on Compact Thin-Film Transistor Modeling (C-TFT)

The 3rd International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation (C-TFT) will be held in Tarragona on July 2 2010.

The C-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London.

Topics:
A partial list of the areas of interest includes:

- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Other details:
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat

Important dates:

- Deadline for abstract submission: May 7, 2010
- Notification of acceptance: May 21, 2010
- Camera-ready version: Jun 18, 2010

This event will be held in coordination with the Training Courses on Compact Modeling (June 30-July 1) and the Graduate Student Meeting on Electronic Engineering (June 28-29).

Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

Training Courses on Compact Modeling: June 30-July 1 2010

The first edition of the Training Courses on Compact Modeling (TCCM) will consist of a set of lectures addressing relevant topics in the compact modeling of advanced electron devices. Most of the courses will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Courses on Compact Modeling are sponsored by the FP7 “COMON” IAPP Project and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


The Training Courses on Compact Modeling will be especially suited to researchers from both industry and academia working on electron device modeling, circuit and systems design and electronic design automated tools. In particular, the courses will be very interesting and useful to students working on these topics.

The General Chair Person is Prof. Benjamin Iñiguez, Universitat Rovira i Virgili, Tarragona, Spain.

The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee.

Topics:

A total of 10 lectures will be conducted. Tthe final programme, with the timetable, will be available soon.
1. Tibor Grasser (TU-Wien) - Transport modeling
2. Tor A Fjeldly (UniK, Norway) - Analytical 2D and 3D electrostatic modeling
3. Jamal Deen (McMaster University, Canada) - Noise modeling
4. Benjamin Iniguez (URV, Spain) - Analytical small-signal modeling
5. Ilcho Angelov (Chalmers University, Sweden) - High frequency device modeling
6. Renaud Gillon (On Semiconductor, Belgium) - Electro-thermal and reliability modeling
7. Sorin Cristoloveanu (MINATEC and LETI, France) - Electrical characterization of SOI and Multi-Gate MOSFETs
8. Asen Asenov (University of Glasgow) - Statistical variability and corresponding compact model strategies
9. Kiyoh Itoh (Hitachi, Japan) - "Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs"
10. Wladek Grabinski - "GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization"

Apr 7, 2010

The Semiconductor Industry’s Nanoelectronics Research Initiative: Motivation and Challenges

Part-2 in the IEEE SCV Electron Devices Society (EDS) "Semiconductor Roadmap and Beyond" series.

Speaker: Dr. Jeffrey Welser, Director, SRC Nanoelectronics Research Initiative

Time: TUESDAY, Apr 13, 2010 6:00 PM - Pizza , 6:15 PM – Lecture

Cost: Free
Location: National Semiconductor
, Building E1, Conference Center ,
2900 Semiconductor Drive , Santa Clara , CA 95051
.
See the NSC Building location map and directions

Contact: Sandeep Bahl

Web link: http://www.ewh.ieee.org/r6/scv/eds/

Apr 6, 2010

Alliance CAD System

Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor: http://alliancecad.sourceforge.net

This project may now be found at http://www-asim.lip6.fr/recherche/alliance/.

Mar 25, 2010

IPL group releases PDK standard

What's next? Under this framework, OpenPDK will base its PDK technology on the OpenAcess database. It will also use several of the components developed by IPL: OA schematic symbols, component description format (CDF) and callbacks. For its part, Si2 will attempt to get the industry to develop standards around several other components: Spice models, tech files and DRC/LVS/LPE. [more]

Mar 22, 2010

Design, Test, Integration & Packaging of MEMS/MOEMS

DTIP 2010, 5-7 May 2010 , Seville, Spain
DTIP 2010 will be a follow-up to the very successful issues held in 1999 and 2000 in Paris and in 2001, 2002 and 2003 in Mandelieu-La Napoule, in 2004 and 2005 in Montreux, Switzerland in 2006, in 2007 in Stresa, Italy, in 2008 in Nice, France and in 2009 in Rome, Italy. This series of Symposia is a unique single-meeting event expressly planned to bring together participants interested in manufacturing microstructures and participants interested in design tools to facilitate the conception of these microstructures. Again, a special emphasis will be put on the very crucial needs of MEMS/MOEMS in terms of packaging solutions. The goal of the Symposium is to provide a forum for in-depth investigations and interdisciplinary discussions involving design, modeling, testing, micromachining, microfabrication, integration and packaging of structures, devices, and systems. The Symposium is sponsored by the IEEE Components, Packaging, and Manufacturing Technology Society and CMP.

Download the call for participation.

Mar 19, 2010

Big Success in Dresden for new DATE 2010

The conference again proved its World-Wide leadership with attendees from 39 Countries. Germany accounts for a fourth of the attendees, followed by USA and France. China showed a substantial increase and was already number 4 of the participating countries. The number of attendees (1,300) again reached the very high level of the previous years [more].

The proceedings of DATE10 are now available on-line.



Mar 17, 2010

[mos-ak] Final Program MOS-AK/GSA Workshop in Rome

Please visit the MOS-AK/Rome Workshop web site:
http://www.mos-ak.org/rome/ with final workshop program

April 8-9, 2010 Sapienza Università di Roma

* Free On-line Registration Form:
http://www.mos-ak.org/rome/index.php#Register

* Venue and Recommended Hotels:
http://www.mos-ak.org/rome/index.php#Venue


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Mar 15, 2010

Angelov FET Model Documents at Uni.Chalmers

New web page with collection of some documents, files and papers on Angelov's FET Large Signal Nonlinear Transistor Mode [link]

Mar 5, 2010

Top 10 cited papers in Solid-State Electronics

I wish to congratulate some friends, because their papers are ranked 4th and 5th in the top 10 cited papers published in Solid-State Electronics... and these are also the first papers in the list about compact modelling...
Many congratulations Adelmo, Francisco, Jean-Michel and Christian !

By the way, the papers are:

Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs

Volume 49, Issue 4, 2005, Pp 640-647
Ortiz-Conde, A. | Sánchez, F.J.G. | Muci, J.


A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism
Volume 49, Issue 3, 2005, Pp 485-489
Sallese, J.-M. | Krummenacher, F. | Prégaldiny, F. | Lallement, C. | Roy, A. | Enz, C.

Mar 2, 2010

Compact TFT Modelling Workshop (C-TFT)

The Third International Workshop on Compact Thin-Film Transistor Modelling (C-TFT) will be held in Tarragona, Spain, on July 2 2010.

This workshop will provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee and the University College London .

Topics:
A partial list of the areas of interest includes:

- Physics of TFTs and operating principles
- Compact TFT device models for circuit simulation
- Model implementation and circuit analysis techniques
- Model parameter extraction techniques
- Applications of compact TFT models in emerging products
- Compact models for interconnects in active matrix flat panels
Other details:
Prospective authors are invited to submit an abstract of up to 500-word to: nae.bogden@urv.cat

Important dates:

- Deadline for abstract submission: May 7, 2010
- Notification of acceptance: May 21, 2010
- Camera-ready version: Jun 18, 2010

Technical comitee members:

General chair person: Prof. Benjamin Iniguez, University Rovira i Virgili, Spain

Rodrigo Picos, Universitat de les Illes Balears, Spain
Bill Milne, Cambridge University, UK
Maria Merlyne De Souza, Sheffield University, UK
Arokia Nathan, University College London, UK
Norbert Fruehauf, University of Stuttgart, Germany
Samar Saha, Silterra Corp., USA
Jamal Deen, McMaster University, Canada
Magali Estrada, CINVESTAV, Mexico
James B. Kuo, National Taiwan University, Taiwan
Hyun Jae Kim, Yonsei University, Korea
Zhou Xing, Nanyang Technological University, Singapore

Local Committee Members:

Benjamin Iniguez, Universitat Rovira i Virgili, Spain
Lluis F. Marsal, Universitat Rovira i Virgili, Spain
Josep Pallares, Universitat Rovira i Virgili, Spain
Josep Ferre, Universitat Rovira i Virgili, Spain
Roger Cabre, Universitat Rovira i Virgili, Spain
Pilar Formentin, Universitat Rovira i Virgili, Spain
Francois Lime, Universitat Rovira i Virgili, Spain
Bogdan Nae, Universitat Rovira i Virgili, Spain

Directions and maps:

University of Rovira i Virgili Campus Map

Tarragona is well connected with the spanish airports of Madrid, Barcelona or Reus by means of trains or buses.

For train tickets, please visit the national railroad company, RENFE. For bus information, please visit La Hispano Igualadina company.


About Tarragona:
Tarragona is located in the south of Catalonia, in the northeast corner of the Iberian Peninsula. Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tarraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

Feb 26, 2010

Lots of Foundries and Fabless Companies do exist - what about standards for their interface?

DATE 2010 ET-P3 PANEL SESSION

Date: Thu, 2010-03-11; Time: 12:45-13:45
Room: Exhibition Theatre, Ground Floor

Organizers: Manfred Dietrich, Fraunhofer IIS/EAS, and Rene Schueffny, TU Dresden

Companies like Broadcom and Nvidia have shown that the Fabless model conquers the semiconductor market. Today all IDM’s use foundries as second source or use it as part of their volume production Because of the high cost of new manufacturing facilities IDM’s become Fablight and concentrate with their production on highly sophisticated processes. How is it possible to handle even more complex circuits if their processes cannot any more be deeply influenced by the internal design team? Today the value chain of the semiconductor market isolates and dominates more and more the vertical companies like EDA, Design house, Fabless, IP provider, Foundry Test & Packaging. Do we have already enough standards or do we need more and where do we need more standards and how can we make it happen? Who will be the driver or who should be the driver? This panel should offer some answers or even create more questions! It is fact - Fabless companies will have more and more impact in the whole IC logic market and Foundries increase their market share every year! Is it time for standards? [more]

Download DATE 2010 Conference Programme (PDF - 3 MB)

Feb 24, 2010

Ultra Low Power Bioelectronics

Fundamentals, Biomedical Applications, and Bio-inspired Systems
Rahul Sarpeshkar; Massachusetts Institute of Technology
Hardback (ISBN-13: 9780521857277)

This book provides, for the first time, a broad and deep treatment of the fields of both ultra low power electronics and bioelectronics. It discusses fundamental principles and circuits for ultra low power electronic design and their applications in biomedical systems. It also discusses how ultra energy efficient cellular and neural systems in biology can inspire revolutionary low power architectures in mixed-signal and RF electronics. The book presents a unique, unifying view of ultra low power analog and digital electronics and emphasizes the use of the ultra energy efficient subthreshold regime of transistor operation in both. Chapters on batteries, energy harvesting, and the future of energy provide an understanding of fundamental relationships between energy use and energy generation at small scales and at large scales. A wealth of insights and examples from brain implants, cochlear implants, bio-molecular sensing, cardiac devices, and bio-inspired systems make the book useful and engaging for students and practicing engineers.

[Table of contents]

Feb 19, 2010

Post-doctoral Research Positions in Healthcare Management

The newly established Collaboration in Healthcare Managemenat Ulm University in Germany invites applications for:

Two Full-Time Post-doctoral Research Positions in Healthcare Management
(or as part-time research/PhD positions for Master’s degree holders)*

Ulm University, a leading medical and natural sciences university in Germany, is seeking two post-doctoral candidates for the newly established collaboration in Healthcare Management. This concentration brings together the medical and the business school at Ulm University to develop expertise in healthcare management. The candidates will work directly for the newly appointed professor of healthcare management and controlling at Ulm University and contribute to developing the teaching and research program. Candidates will participate in domestic and international collaborations with leading academic and medical institutions. Ideal candidates will possess academic or practical healthcare management experience and an understanding of the healthcare market, but need not come from a healthcare background. Candidates can expect the position to open doors for healthcare administration in Europe and the U.S.

To apply: Please send CV, cover letter, a brief synopsis of a research project previously conducted (or up to three selected publications) and up to 3 letters of reference to Prof. Dr. Katharina Janus latest until March 11, 2010.

[more]

*Non-PhD holders:

Candidates without a PhD have the option to complete a PhD at Ulm University while working part-time in the described positions. The professor of health management and controlling will act as the PhD candidate’s academic supervisor. To enroll in the PhD, candidates need to hold a Master’s Degree in a related field and propose an adequate research topic to the academic supervisor.

Feb 18, 2010

PhD Studentship Available in Scanning Probe Microscopy of Biomolecular Surfaces - Dublin, Ireland

Investigating Electrostatic Interactions in Biomolecular Systems at the Nanoscale

Nanoscale characterization of electric charge and electric surface potentials in biomolecular systems is critical for understanding biomolecular interactions. Changes in surface potential dictate cellular-membrane transport and thus provide a crucial pathway for cells to interact with their environment. This project will focus on investigating electrostatic interactions at biological surfaces using a scanning probe approach. Mapping electrostatic interactions in biological systems may provide a pathway to understand the role of charge in biological processes.

This interdisciplinary project will provide training in advanced ambient and liquid, structural and functional imaging using an atomic force microscope (AFM) and in biological sample preparation. The successful applicant will be involved in the further development of advanced scanning probe techniques and novel shielded AFM probes and is expected to develop and publish their work and to present their work at national and international conferences. He/She will have access to state of the art AFMs, and will be expected to work closely with the Nanoscale Function Group of Prof. Suzi Jarvis. Travel opportunities to interact with collaborating researchers and industrial partners are also envisaged.

Funding is available for up to 4 years and includes a stipend of €15k per annum, plus EUfees.Location: UCD Conway Institute of Biomolecular and Biomedical Research, Dublin, Ireland

Qualification: Candidates should have or expect to obtain a first or upper second BSc (or equivalent) or MSc in Physics, Materials Science, Biology, or a related area.

Funding is restricted to EU applicants only.

More information: http://www.nanopaprika.eu/profiles/blogs/phd-studentship-available-in

MIXDES 2010 paper submission deadline - less than 2 weeks left

I would like to kindly remind you that there is less than 2 weeks left for regular paper submission for MIXDES 2010 Conference. If you have any remaining papers which has not been submitted yet, I kindly ask you to do so before the deadline expiration. 
 
Please note that the papers should be registered and submitted from the conference website (www.mixdes.org).
If you any problems with registration, please report it the MIXDES Conference Secretary (mixdes2010@dmcs.p.lodz.pl) ASAP.